mirror of https://github.com/YosysHQ/yosys.git
Do not create $dffsr cells with no-op resets in proc_dff
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@ -356,6 +356,11 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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rstval.optimize();
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sig.optimize();
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if (rstval == sig) {
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rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width);
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sync_level = NULL;
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}
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if (sync_always) {
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if (sync_edge || sync_level || many_async_rules.size() > 0)
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log_error("Mixed always event with edge and/or level sensitive events!\n");
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