mirror of https://github.com/YosysHQ/yosys.git
Implemented extract -mine_max_fanout <num> option
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f9a5fbf283
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@ -36,7 +36,7 @@ namespace
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int bit;
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};
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bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel = NULL)
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bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel = NULL, int max_fanout = -1)
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{
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SigMap sigmap(mod);
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std::map<RTLIL::SigChunk, bit_ref_t> sig_bit_ref;
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@ -66,6 +66,22 @@ namespace
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graph.markExtern("$const$z", "\\Y", 0);
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}
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std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
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if (max_fanout > 0)
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for (auto &cell_it : mod->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (!sel || sel->selected(mod, cell))
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for (auto &conn : cell->connections) {
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RTLIL::SigSpec conn_sig = conn.second;
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sigmap.apply(conn_sig);
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conn_sig.expand();
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for (auto &chunk : conn_sig.chunks)
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if (chunk.wire != NULL)
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sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++;
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}
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}
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// create graph nodes from cells
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for (auto &cell_it : mod->cells)
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{
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@ -102,6 +118,9 @@ namespace
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continue;
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}
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if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)] > max_fanout)
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continue;
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if (sig_bit_ref.count(chunk) == 0) {
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bit_ref_t &bit_ref = sig_bit_ref[chunk];
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bit_ref.cell = cell->name;
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@ -282,6 +301,9 @@ struct ExtractPass : public Pass {
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log(" when calculating the number of matches for a subcircuit, don't count\n");
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log(" more than the specified number of matches per module\n");
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log("\n");
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log(" -mine_max_fanout <num>\n");
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log(" don't consider internal signals with more than <num> connections\n");
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log("\n");
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log("The modules in the map file may have the attribute 'extract_order' set to an\n");
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log("integer value. Then this value is used to determine the order in which the pass\n");
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log("tries to map the modules to the design (ascending, default value is 0).\n");
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@ -308,6 +330,7 @@ struct ExtractPass : public Pass {
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int mine_cells_max = 10;
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int mine_min_freq = 10;
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int mine_limit_mod = -1;
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int mine_max_fanout = -1;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -333,6 +356,10 @@ struct ExtractPass : public Pass {
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mine_limit_mod = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-mine_max_fanout" && argidx+1 < args.size()) {
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mine_max_fanout = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-verbose") {
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solver.setVerbose();
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continue;
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@ -440,7 +467,7 @@ struct ExtractPass : public Pass {
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SubCircuit::Graph mod_graph;
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std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
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log("Creating haystack graph %s.\n", graph_name.c_str());
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if (module2graph(mod_graph, mod_it.second, constports, design)) {
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if (module2graph(mod_graph, mod_it.second, constports, design, mine_mode ? mine_max_fanout : -1)) {
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solver.addGraph(graph_name, mod_graph);
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haystack_map[graph_name] = mod_it.second;
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}
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