mirror of https://github.com/YosysHQ/yosys.git
Bugfix in iopadmap
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@ -114,18 +114,11 @@ struct IopadmapPass : public Pass {
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}
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extra_args(args, argidx, design);
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for (auto &it : design->modules_)
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for (auto module : design->selected_modules())
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{
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RTLIL::Module *module = it.second;
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if (!design->selected(module) || module->get_bool_attribute("\\blackbox"))
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continue;
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for (auto &it2 : module->wires_)
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for (auto wire : module->selected_wires())
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{
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RTLIL::Wire *wire = it2.second;
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if (!wire->port_id || !design->selected(module, wire))
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if (!wire->port_id)
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continue;
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std::string celltype, portname, portname2;
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