mirror of https://github.com/YosysHQ/yosys.git
Replace -ignore_redef with -[no]overwrite
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
e060375f23
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a572b49538
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@ -1003,7 +1003,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
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// create AstModule instances for all modules in the AST tree and add them to 'design'
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
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{
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current_ast = ast;
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flag_dump_ast1 = dump_ast1;
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@ -1042,12 +1042,20 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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(*it)->str = "$abstract" + (*it)->str;
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if (design->has((*it)->str)) {
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if (!ignore_redef)
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RTLIL::Module *existing_mod = design->module((*it)->str);
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if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
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log_error("Re-definition of module `%s' at %s:%d!\n",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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log("Ignoring re-definition of module `%s' at %s:%d!\n",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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continue;
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} else if (nooverwrite) {
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log("Ignoring re-definition of module `%s' at %s:%d.\n",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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continue;
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} else {
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log("Replacing existing%s module `%s' at %s:%d.\n",
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existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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design->remove(existing_mod);
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}
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}
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design->add(process_module(*it, defer));
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@ -275,7 +275,7 @@ namespace AST
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
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bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
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bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
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// parametric modules are supported directly by the AST library
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// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
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@ -463,9 +463,13 @@ struct LibertyFrontend : public Frontend {
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log(" -lib\n");
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log(" only create empty blackbox modules\n");
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log("\n");
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log(" -ignore_redef\n");
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log(" -nooverwrite\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message.)\n");
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log(" create an error message if the existing module is not a blackbox\n");
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log(" module, and overwrite the existing module if it is a blackbox module.)\n");
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log("\n");
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log(" -overwrite\n");
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log(" overwrite existing modules with the same name\n");
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log("\n");
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log(" -ignore_miss_func\n");
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log(" ignore cells with missing function specification of outputs\n");
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@ -484,7 +488,8 @@ struct LibertyFrontend : public Frontend {
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virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_lib = false;
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bool flag_ignore_redef = false;
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bool flag_nooverwrite = false;
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bool flag_overwrite = false;
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bool flag_ignore_miss_func = false;
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bool flag_ignore_miss_dir = false;
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bool flag_ignore_miss_data_latch = false;
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@ -499,8 +504,14 @@ struct LibertyFrontend : public Frontend {
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flag_lib = true;
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continue;
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}
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if (arg == "-ignore_redef") {
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flag_ignore_redef = true;
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if (arg == "-ignore_redef" || arg == "-nooverwrite") {
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flag_nooverwrite = true;
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flag_overwrite = false;
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continue;
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}
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if (arg == "-overwrite") {
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flag_nooverwrite = false;
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flag_overwrite = true;
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continue;
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}
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if (arg == "-ignore_miss_func") {
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@ -537,9 +548,16 @@ struct LibertyFrontend : public Frontend {
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std::string cell_name = RTLIL::escape_id(cell->args.at(0));
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if (design->has(cell_name)) {
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if (flag_ignore_redef)
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Module *existing_mod = design->module(cell_name);
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if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
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log_error("Re-definition of of cell/module %s!\n", log_id(cell_name));
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} else if (flag_nooverwrite) {
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log("Ignoring re-definition of module %s.\n", log_id(cell_name));
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continue;
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log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str());
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} else {
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log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name));
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design->remove(existing_mod);
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}
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}
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// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
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@ -137,9 +137,13 @@ struct VerilogFrontend : public Frontend {
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log(" -icells\n");
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log(" interpret cell types starting with '$' as internal cell types\n");
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log("\n");
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log(" -ignore_redef\n");
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log(" -nooverwrite\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message.)\n");
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log(" create an error message if the existing module is not a black box\n");
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log(" module, and overwrite the existing module otherwise.)\n");
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log("\n");
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log(" -overwrite\n");
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log(" overwrite existing modules with the same name\n");
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log("\n");
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log(" -defer\n");
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log(" only read the abstract syntax tree and defer actual compilation\n");
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@ -191,7 +195,8 @@ struct VerilogFrontend : public Frontend {
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bool flag_nodpi = false;
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bool flag_noopt = false;
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bool flag_icells = false;
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bool flag_ignore_redef = false;
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bool flag_nooverwrite = false;
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bool flag_overwrite = false;
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bool flag_defer = false;
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std::map<std::string, std::string> defines_map;
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std::list<std::string> include_dirs;
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@ -289,8 +294,14 @@ struct VerilogFrontend : public Frontend {
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flag_icells = true;
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continue;
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}
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if (arg == "-ignore_redef") {
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flag_ignore_redef = true;
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if (arg == "-ignore_redef" || arg == "-nooverwrite") {
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flag_nooverwrite = true;
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flag_overwrite = false;
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continue;
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}
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if (arg == "-overwrite") {
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flag_nooverwrite = false;
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flag_overwrite = true;
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continue;
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}
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if (arg == "-defer") {
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@ -370,7 +381,7 @@ struct VerilogFrontend : public Frontend {
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if (flag_nodpi)
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error_on_dpi_function(current_ast);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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delete lexin;
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@ -933,7 +933,7 @@ struct TechmapPass : public Pass {
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log(" -D <define>, -I <incdir>\n");
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log(" this options are passed as-is to the Verilog frontend for loading the\n");
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log(" map file. Note that the Verilog frontend is also called with the\n");
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log(" '-ignore_redef' option set.\n");
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log(" '-nooverwrite' option set.\n");
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log("\n");
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log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
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log("match cells with a type that match the text value of this attribute. Otherwise\n");
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@ -1031,7 +1031,7 @@ struct TechmapPass : public Pass {
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simplemap_get_mappers(worker.simplemap_mappers);
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std::vector<std::string> map_files;
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std::string verilog_frontend = "verilog -ignore_redef";
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std::string verilog_frontend = "verilog -nooverwrite";
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int max_iter = -1;
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size_t argidx;
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