riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix spacing

This commit is contained in:
Eddie Hung 2019-06-26 20:03:34 -07:00
parent 080a5ca536
commit c226af3f56
1 changed files with 37 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
passes/techmap/abc9.cc
View File

@ -116,45 +116,45 @@ void handle_loops(RTLIL::Design *design)
cell->attributes.erase(it);
}
auto jt = module_break.find(cell->type);
auto jt = module_break.find(cell->type);
if (jt == module_break.end()) {
std::vector<IdString> ports;
if (!yosys_celltypes.cell_known(cell->type)) {
RTLIL::Module* box_module = design->module(cell->type);
log_assert(box_module);
auto ports_csv = box_module->attributes.at("\\abc_scc_break", RTLIL::Const::from_string("")).decode_string();
for (const auto &port_name : split_tokens(ports_csv, ",")) {
auto port_id = RTLIL::escape_id(port_name);
auto kt = cell->connections_.find(port_id);
if (kt == cell->connections_.end())
log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", port_name.c_str(), log_id(box_module));
ports.push_back(port_id);
}
}
jt = module_break.insert(std::make_pair(cell->type, std::move(ports))).first;
}
std::vector<IdString> ports;
if (!yosys_celltypes.cell_known(cell->type)) {
RTLIL::Module* box_module = design->module(cell->type);
log_assert(box_module);
auto ports_csv = box_module->attributes.at("\\abc_scc_break", RTLIL::Const::from_string("")).decode_string();
for (const auto &port_name : split_tokens(ports_csv, ",")) {
auto port_id = RTLIL::escape_id(port_name);
auto kt = cell->connections_.find(port_id);
if (kt == cell->connections_.end())
log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", port_name.c_str(), log_id(box_module));
ports.push_back(port_id);
}
}
jt = module_break.insert(std::make_pair(cell->type, std::move(ports))).first;
}
for (auto port_name : jt->second) {
RTLIL::SigSpec sig;
auto &rhs = cell->connections_.at(port_name);
for (auto b : rhs) {
Wire *w = b.wire;
if (!w) continue;
w->port_output = true;
w->set_bool_attribute("\\abc_scc_break");
w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
w->port_input = true;
}
else {
log_assert(b.offset < GetSize(w));
log_assert(w->port_input);
}
sig.append(RTLIL::SigBit(w, b.offset));
}
rhs = sig;
}
for (auto port_name : jt->second) {
RTLIL::SigSpec sig;
auto &rhs = cell->connections_.at(port_name);
for (auto b : rhs) {
Wire *w = b.wire;
if (!w) continue;
w->port_output = true;
w->set_bool_attribute("\\abc_scc_break");
w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
w->port_input = true;
}
else {
log_assert(b.offset < GetSize(w));
log_assert(w->port_input);
}
sig.append(RTLIL::SigBit(w, b.offset));
}
rhs = sig;
}
}
module->fixup_ports();