Removed $predict again

examples/smtbmc/demo1.v

@@ -10,7 +10,6 @@ module demo1(input clk, input addtwo, output iseven);
 `ifdef FORMAL
 	assert property (cnt != 15);
 	initial assume (!cnt[3] && !cnt[0]);
-	// initial predict ((iseven && addtwo) || cnt == 9);
 `endif
 endmodule
 

frontends/ast/ast.cc

@@ -83,7 +83,6 @@ std::string AST::type2str(AstNodeType type)
 	X(AST_PREFIX)
 	X(AST_ASSERT)
 	X(AST_ASSUME)
-	X(AST_PREDICT)
 	X(AST_FCALL)
 	X(AST_TO_BITS)
 	X(AST_TO_SIGNED)

frontends/ast/ast.h

@@ -65,7 +65,6 @@ namespace AST
 		AST_PREFIX,
 		AST_ASSERT,
 		AST_ASSUME,
-		AST_PREDICT,
 
 		AST_FCALL,
 		AST_TO_BITS,

frontends/ast/genrtlil.cc

@@ -1317,11 +1317,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// generate $assert cells
 	case AST_ASSERT:
 	case AST_ASSUME:
-	case AST_PREDICT:
 		{
 			const char *celltype = "$assert";
 			if (type == AST_ASSUME) celltype = "$assume";
-			if (type == AST_PREDICT) celltype = "$predict";
 
 			log_assert(children.size() == 2);
 

frontends/ast/simplify.cc

@@ -1352,7 +1352,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	}
 skip_dynamic_range_lvalue_expansion:;
 
-	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && current_block != NULL)
+	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL)
 	{
 		std::stringstream sstr;
 		sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@@ -1414,7 +1414,7 @@ skip_dynamic_range_lvalue_expansion:;
 		goto apply_newNode;
 	}
 
-	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && children.size() == 1)
+	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1)
 	{
 		children.push_back(mkconst_int(1, false, 1));
 		did_something = true;

frontends/verilog/verilog_lexer.l

@@ -178,7 +178,6 @@ YOSYS_NAMESPACE_END
 "assert"   { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
 "assume"   { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
 "restrict" { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
-"predict"  { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 "logic"    { SV_KEYWORD(TOK_REG); }
 "bit"      { SV_KEYWORD(TOK_REG); }

frontends/verilog/verilog_parser.y

@@ -114,7 +114,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
-%token TOK_RESTRICT TOK_PREDICT TOK_PROPERTY
+%token TOK_RESTRICT TOK_PROPERTY
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@@ -1006,9 +1006,6 @@ assert:
 			delete $3;
 		else
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
-	} |
-	TOK_PREDICT '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $3));
 	};
 
 assert_property:
@@ -1023,9 +1020,6 @@ assert_property:
 			delete $4;
 		else
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
-	} |
-	TOK_PREDICT TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $4));
 	};
 
 simple_behavioral_stmt:

kernel/celltypes.h

@@ -116,7 +116,6 @@ struct CellTypes
 
 		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
 		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
 		setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
 		setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
 		setup_type("$aconst", pool<RTLIL::IdString>(), {Y}, true);

kernel/rtlil.cc

@@ -1017,7 +1017,7 @@ namespace {
 				return;
 			}
 
-			if (cell->type.in("$assert", "$assume", "$predict")) {
+			if (cell->type.in("$assert", "$assume")) {
 				port("\\A", 1);
 				port("\\EN", 1);
 				check_expected();
@@ -1809,14 +1809,6 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	return cell;
 }
 
-RTLIL::Cell* RTLIL::Module::addExpect(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
-{
-	RTLIL::Cell *cell = addCell(name, "$predict");
-	cell->setPort("\\A", sig_a);
-	cell->setPort("\\EN", sig_en);
-	return cell;
-}
-
 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
 {
 	RTLIL::Cell *cell = addCell(name, "$equiv");

kernel/rtlil.h

@@ -1005,7 +1005,6 @@ public:
 	RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y);
 	RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
 	RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
-	RTLIL::Cell* addExpect (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
 	RTLIL::Cell* addEquiv  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
 
 	RTLIL::Cell* addSr    (RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true);

manual/CHAPTER_CellLib.tex

@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells.
 \end{fixme}
 
 \begin{fixme}

passes/hierarchy/hierarchy.cc

@@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 	if (cache.count(mod) == 0)
 		for (auto c : mod->cells()) {
 			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$predict"))
+			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume"))
 				return cache[mod] = true;
 		}
 	return cache[mod];

passes/opt/opt_clean.cc

@@ -64,7 +64,7 @@ struct keep_cache_t
 
 	bool query(Cell *cell)
 	{
-		if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$predict"))
+		if (cell->type.in("$memwr", "$meminit", "$assert", "$assume"))
 			return true;
 
 		if (cell->has_keep_attr())

passes/tests/test_cell.cc

@@ -854,7 +854,6 @@ struct TestCellPass : public Pass {
 		// cell_types["$concat"] = "A";
 		// cell_types["$assert"] = "A";
 		// cell_types["$assume"] = "A";
-		// cell_types["$predict"] = "A";
 
 		cell_types["$lut"] = "*";
 		cell_types["$sop"] = "*";

techlibs/common/simlib.v

@@ -1305,14 +1305,6 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$predict (A, EN);
-
-input A, EN;
-
-endmodule
-
-// --------------------------------------------------------
-
 module \$initstate (Y);
 
 output reg Y = 1;