mirror of https://github.com/YosysHQ/yosys.git
Renamed "sat_solve" pass to "sat"
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@ -1,3 +1,3 @@
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OBJS += passes/sat/sat_solve.o
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OBJS += passes/sat/sat.o
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@ -2,12 +2,12 @@
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read_verilog example.v
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proc; opt_clean
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sat_solve -set y 1'b1 example001
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sat_solve -set y 1'b1 example002
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sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
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sat_solve -set y 1'b1 example004
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sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
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sat -set y 1'b1 example001
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sat -set y 1'b1 example002
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sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
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sat -set y 1'b1 example004
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sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
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sat_solve -prove y 1'b0 -show rst,counter,y example004
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sat_solve -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004
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sat -prove y 1'b0 -show rst,counter,y example004
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sat -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004
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@ -469,13 +469,13 @@ static void print_qed()
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log("\n");
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}
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struct SatSolvePass : public Pass {
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SatSolvePass() : Pass("sat_solve", "solve a SAT problem in the circuit") { }
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struct SatPass : public Pass {
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SatPass() : Pass("sat", "solve a SAT problem in the circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sat_solve [options] [selection]\n");
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log(" sat [options] [selection]\n");
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log("\n");
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log("This command solves a SAT problem defined over the currently selected circuit\n");
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log("and additional constraints passed as parameters.\n");
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@ -749,5 +749,5 @@ struct SatSolvePass : public Pass {
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}
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}
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}
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} SatSolvePass;
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} SatPass;
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