mirror of https://github.com/YosysHQ/yosys.git
Added design->select() api and use it in extract pass
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@ -212,6 +212,13 @@ struct RTLIL::Design {
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template<typename T1, typename T2> bool selected(T1 *module, T2 *member) {
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return selected_member(module->name, member->name);
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}
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template<typename T1, typename T2> void select(T1 *module, T2 *member) {
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if (selection_stack.size() > 0) {
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RTLIL::Selection &sel = selection_stack.back();
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if (!sel.full_selection && sel.selected_modules.count(module->name) == 0)
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sel.selected_members[module->name].insert(member->name);
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}
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}
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};
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struct RTLIL::Module {
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@ -156,7 +156,7 @@ namespace
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return true;
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}
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void replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
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RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
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{
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SigMap sigmap(needle);
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SigSet<std::pair<std::string, int>> sig2port;
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@ -202,6 +202,8 @@ namespace
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haystack->cells.erase(haystack_cell->name);
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delete haystack_cell;
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}
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return cell;
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}
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}
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@ -451,7 +453,9 @@ struct ExtractPass : public Pass {
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log(" %s:%s", it2.first.c_str(), it2.second.c_str());
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log("\n");
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}
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replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
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RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
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design->select(haystack_map.at(result.haystackGraphId), new_cell);
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log(" new cell: %s\n", id2cstr(new_cell->name));
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}
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}
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}
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