mirror of https://github.com/YosysHQ/yosys.git
Added techmap support for _TECHMAP_CONNMAP_*_
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@ -271,6 +271,37 @@ struct TechmapWorker
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parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
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}
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}
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int unique_bit_id_counter = 0;
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std::map<RTLIL::SigBit, int> unique_bit_id;
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unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
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unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
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unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
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unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
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for (auto conn : cell->connections)
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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for (auto &bit : sigmap(conn.second).to_sigbit_vector())
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if (unique_bit_id.count(bit) == 0)
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unique_bit_id[bit] = unique_bit_id_counter++;
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}
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int bits = 0;
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for (int i = 0; i < 32; i++)
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if (((unique_bit_id_counter-1) & (1 << i)) != 0)
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bits = i;
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if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
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parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
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for (auto conn : cell->connections)
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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RTLIL::Const value;
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for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
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RTLIL::Const chunk(unique_bit_id.at(bit), bits);
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value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
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}
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parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
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}
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}
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
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@ -468,6 +499,14 @@ struct TechmapPass : public Pass {
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log(" former has a 1-bit for each constant input bit and the latter has the\n");
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log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
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log("\n");
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log(" _TECHMAP_BITS_CONNMAP_\n");
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log(" _TECHMAP_CONNMAP_<port-name>_\n");
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log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
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log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
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log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
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log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
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log(" This can be used to detect shorted inputs.\n");
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log("\n");
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log("When a module in the map file has a parameter where the according cell in the\n");
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log("design has a port, the module from the map file is only used if the port in\n");
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log("the design is connected to a constant value. The parameter is then set to the\n");
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