riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed typo in test_cell

This commit is contained in:
Clifford Wolf 2014-10-18 16:52:06 +01:00
parent 6bcb4f1f45
commit 41db98ba31
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/tests/test_cell.cc
View File

@ -522,7 +522,7 @@ struct TestCellPass : public Pass {
log(" -map {filename}\n");
log(" pass this option to techmap.\n");
log("\n");
log(" -simplib\n");
log(" -simlib\n");
log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
log("\n");
log(" -script {script_file}\n");