mirror of https://github.com/YosysHQ/yosys.git
Added -format option to splitnets
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6bfeb17f05
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613750155d
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@ -48,6 +48,11 @@ struct SplitnetsPass : public Pass {
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log("\n");
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log("This command splits multi-bit nets into single-bit nets.\n");
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log("\n");
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log(" -format char1[char2]\n");
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log(" the first char is inserted between the net name and the bit index, the\n");
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log(" second char is appended to the netname. e.g. -format () creates net\n");
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log(" names like 'mysignal(42)'. the default is '[]'.\n");
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log("\n");
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log(" -ports\n");
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log(" also split module ports. per default only internal signals are split.\n");
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log("\n");
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@ -55,10 +60,15 @@ struct SplitnetsPass : public Pass {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_ports = false;
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std::string format = "[]";
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-format" && argidx+1 < args.size()) {
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format = args[++argidx];
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continue;
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}
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if (args[argidx] == "-ports") {
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flag_ports = true;
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continue;
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@ -87,7 +97,12 @@ struct SplitnetsPass : public Pass {
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wire->port_id = it.first->port_id;
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wire->port_input = it.first->port_input;
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wire->port_output = it.first->port_output;
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wire->name = it.first->name + stringf("[%d]", i);
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wire->name = it.first->name;
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if (format.size() > 0)
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wire->name += format.substr(0, 1);
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wire->name += stringf("%d", i);
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if (format.size() > 0)
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wire->name += format.substr(1);
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while (module->count_id(wire->name) > 0)
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wire->name = wire->name + "_";
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module->add(wire);
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