mirror of https://github.com/YosysHQ/yosys.git
Fixed/improved opt_const $eq/$ne/$eqx/$nex handling
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@ -166,6 +166,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
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continue;
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}
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if (a.chunks[i] == b.chunks[i])
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continue;
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new_a.append(a.chunks[i]);
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new_b.append(b.chunks[i]);
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}
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@ -177,7 +179,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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goto next_cell;
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}
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if (new_a.width != a.width) {
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if (new_a.width < a.width || new_b.width < b.width) {
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new_a.optimize();
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new_b.optimize();
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cell->connections["\\A"] = new_a;
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