mirror of https://github.com/YosysHQ/yosys.git
Cope with $reduce_or common in case
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32f637ffdb
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@ -29,11 +29,13 @@ struct ExclusiveDatabase
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Module *module;
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const SigMap &sigmap;
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dict<SigBit, std::pair<SigSpec,Const>> sig_cmp_prev;
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dict<SigBit, std::pair<SigSpec,std::vector<Const>>> sig_cmp_prev;
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ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
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{
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SigSpec const_sig, nonconst_sig, y_port;
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SigSpec const_sig, nonconst_sig;
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SigBit y_port;
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pool<Cell*> reduce_or;
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for (auto cell : module->cells()) {
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if (cell->type == "$eq") {
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nonconst_sig = sigmap(cell->getPort("\\A"));
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@ -50,11 +52,40 @@ struct ExclusiveDatabase
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const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
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y_port = sigmap(cell->getPort("\\Y"));
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}
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else if (cell->type == "$reduce_or") {
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reduce_or.insert(cell);
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continue;
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}
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else continue;
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log_assert(!nonconst_sig.empty());
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log_assert(!const_sig.empty());
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sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
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sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::vector<Const>{const_sig.as_const()});
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}
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for (auto cell : reduce_or) {
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nonconst_sig = SigSpec();
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std::vector<Const> values;
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SigSpec a_port = sigmap(cell->getPort("\\A"));
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for (auto bit : a_port) {
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auto it = sig_cmp_prev.find(bit);
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if (it == sig_cmp_prev.end()) {
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nonconst_sig = SigSpec();
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break;
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}
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if (nonconst_sig.empty())
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nonconst_sig = it->second.first;
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else if (nonconst_sig != it->second.first) {
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nonconst_sig = SigSpec();
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break;
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}
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for (auto value : it->second.second)
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values.push_back(value);
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}
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if (nonconst_sig.empty())
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continue;
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y_port = sigmap(cell->getPort("\\Y"));
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sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values));
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}
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}
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@ -73,8 +104,9 @@ struct ExclusiveDatabase
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else if (nonconst_sig != it->second.first)
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return false;
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if (!const_values.insert(it->second.second).second)
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return false;
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for (auto value : it->second.second)
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if (!const_values.insert(value).second)
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return false;
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}
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return true;
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