mirror of https://github.com/YosysHQ/yosys.git
Changed more code to the new RTLIL::Wire constructors
This commit is contained in:
Clifford Wolf
parent
946ddff9ce
commit
d68c993ed2
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@ -777,7 +777,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
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new_mod->attributes = attributes;
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for (auto &it : wires)
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new_mod->wires[it.first] = new RTLIL::Wire(*it.second);
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new_mod->addWire(it.first, it.second);
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for (auto &it : memories)
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new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
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@ -952,6 +952,18 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
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return wire;
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}
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RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
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{
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RTLIL::Wire *wire = addWire(name);
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wire->width = other->width;
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wire->start_offset = other->start_offset;
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wire->port_id = other->port_id;
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wire->port_input = other->port_input;
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wire->port_output = other->port_output;
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wire->attributes = other->attributes;
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return wire;
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}
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RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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@ -273,6 +273,11 @@ struct RTLIL::Design {
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struct RTLIL::Module
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{
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protected:
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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public:
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RTLIL::IdString name;
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std::set<RTLIL::IdString> avail_parameters;
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std::map<RTLIL::IdString, RTLIL::Wire*> wires;
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@ -297,9 +302,6 @@ struct RTLIL::Module
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void cloneInto(RTLIL::Module *new_mod) const;
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virtual RTLIL::Module *clone() const;
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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// Removing wires is expensive. If you have to remove wires, remove them all at once.
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void remove(const std::set<RTLIL::Wire*> &wires);
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void remove(RTLIL::Cell *cell);
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@ -309,6 +311,8 @@ struct RTLIL::Module
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void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
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RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
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RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
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RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
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RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
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@ -445,7 +449,7 @@ struct RTLIL::Module
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struct RTLIL::Wire
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{
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//protected:
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protected:
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// use module->addWire() and module->remove() to create or destroy wires
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friend struct RTLIL::Module;
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Wire();
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@ -453,8 +457,8 @@ struct RTLIL::Wire
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public:
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// do not simply copy wires
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//Wire(RTLIL::Wire &other) = delete;
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//void operator=(RTLIL::Wire &other) = delete;
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Wire(RTLIL::Wire &other) = delete;
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void operator=(RTLIL::Wire &other) = delete;
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RTLIL::IdString name;
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int width, start_offset, port_id;
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@ -31,21 +31,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
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for (auto &it : module->wires)
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if (it.first == from_name) {
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RTLIL::Wire *wire = it.second;
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log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str());
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module->wires.erase(wire->name);
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wire->name = to_name;
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module->add(wire);
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log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
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module->rename(it.second, to_name);
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return;
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}
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for (auto &it : module->cells)
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if (it.first == from_name) {
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RTLIL::Cell *cell = it.second;
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log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str());
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module->cells.erase(cell->name);
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cell->name = to_name;
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module->add(cell);
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log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
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module->rename(it.second, to_name);
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return;
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}
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@ -224,14 +224,14 @@ struct SpliceWorker
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for (auto &it : rework_wires)
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{
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module->wires.erase(it.first->name);
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RTLIL::Wire *new_port = new RTLIL::Wire(*it.first);
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it.first->name = NEW_ID;
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std::string orig_name = it.first->name;
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module->rename(it.first, NEW_ID);
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RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
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it.first->port_id = 0;
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it.first->port_input = false;
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it.first->port_output = false;
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module->add(it.first);
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module->add(new_port);
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module->connect(RTLIL::SigSig(new_port, it.second));
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}
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}
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@ -208,11 +208,11 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
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}
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}
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static void add_new_wire(RTLIL::Module *module, RTLIL::Wire *wire)
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static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1)
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{
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if (module->count_id(wire->name))
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log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", RTLIL::id2cstr(wire->name));
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module->add(wire);
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if (module->count_id(name))
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log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
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return module->addWire(name, width);
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}
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struct ExposePass : public Pass {
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@ -448,7 +448,6 @@ struct ExposePass : public Pass {
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SigMap sigmap(module);
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SigMap out_to_in_map;
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std::vector<RTLIL::Wire*> new_wires;
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for (auto &it : module->wires)
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{
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@ -468,20 +467,14 @@ struct ExposePass : public Pass {
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}
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if (flag_cut) {
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RTLIL::Wire *in_wire = new RTLIL::Wire;
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in_wire->name = it.second->name + sep + "i";
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in_wire->width = it.second->width;
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RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width);
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in_wire->port_input = true;
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out_to_in_map.add(sigmap(it.second), in_wire);
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new_wires.push_back(in_wire);
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}
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}
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if (flag_cut)
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{
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for (auto it : new_wires)
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add_new_wire(module, it);
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for (auto &it : module->cells) {
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if (!ct.cell_known(it.second->type))
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continue;
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@ -507,10 +500,7 @@ struct ExposePass : public Pass {
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dff_map_info_t &info = dq.second;
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RTLIL::Wire *wire_dummy_q = new RTLIL::Wire;
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wire_dummy_q->name = NEW_ID;
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wire_dummy_q->width = 0;
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add_new_wire(module, wire_dummy_q);
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RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
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for (auto &cell_name : info.cells) {
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RTLIL::Cell *cell = module->cells.at(cell_name);
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@ -521,12 +511,9 @@ struct ExposePass : public Pass {
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cell->set("\\Q", cell_q_bits);
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}
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RTLIL::Wire *wire_q = new RTLIL::Wire;
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wire_q->name = wire->name + sep + "q";
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wire_q->width = wire->width;
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RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width);
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wire_q->port_input = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
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add_new_wire(module, wire_q);
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RTLIL::SigSig connect_q;
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for (size_t i = 0; i < wire_bits_vec.size(); i++) {
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@ -538,19 +525,14 @@ struct ExposePass : public Pass {
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}
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module->connect(connect_q);
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RTLIL::Wire *wire_d = new RTLIL::Wire;
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wire_d->name = wire->name + sep + "d";
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wire_d->width = wire->width;
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RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width);
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wire_d->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
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add_new_wire(module, wire_d);
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module->connect(RTLIL::SigSig(wire_d, info.sig_d));
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RTLIL::Wire *wire_c = new RTLIL::Wire;
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wire_c->name = wire->name + sep + "c";
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RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c");
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wire_c->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
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add_new_wire(module, wire_c);
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if (info.clk_polarity) {
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module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
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} else {
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@ -564,11 +546,9 @@ struct ExposePass : public Pass {
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if (info.sig_arst != RTLIL::State::Sm)
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{
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RTLIL::Wire *wire_r = new RTLIL::Wire;
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wire_r->name = wire->name + sep + "r";
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RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r");
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wire_r->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
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add_new_wire(module, wire_r);
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if (info.arst_polarity) {
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module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
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} else {
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@ -580,12 +560,9 @@ struct ExposePass : public Pass {
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c->set("\\Y", wire_r);
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}
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RTLIL::Wire *wire_v = new RTLIL::Wire;
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wire_v->name = wire->name + sep + "v";
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wire_v->width = wire->width;
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RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width);
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wire_v->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
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add_new_wire(module, wire_v);
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module->connect(RTLIL::SigSig(wire_v, info.arst_value));
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}
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}
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@ -616,14 +593,11 @@ struct ExposePass : public Pass {
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if (!p->port_input && !p->port_output)
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continue;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = cell->name + sep + RTLIL::unescape_id(p->name);
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w->width = p->width;
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RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width);
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if (p->port_input)
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w->port_output = true;
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if (p->port_output)
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w->port_input = true;
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add_new_wire(module, w);
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log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
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@ -641,14 +615,11 @@ struct ExposePass : public Pass {
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{
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for (auto &it : cell->connections())
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{
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = cell->name + sep + RTLIL::unescape_id(it.first);
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w->width = it.second.size();
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RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size());
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if (ct.cell_input(cell->type, it.first))
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w->port_output = true;
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if (ct.cell_output(cell->type, it.first))
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w->port_input = true;
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add_new_wire(module, w);
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log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
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@ -729,13 +729,10 @@ struct ExtractPass : public Pass {
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int portCounter = 1;
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for (auto wire : wires) {
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RTLIL::Wire *newWire = new RTLIL::Wire;
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newWire->name = wire->name;
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newWire->width = wire->width;
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RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
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newWire->port_id = portCounter++;
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newWire->port_input = true;
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newWire->port_output = true;
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newMod->add(newWire);
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}
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for (auto cell : cells) {
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@ -164,13 +164,8 @@ struct IopadmapPass : public Pass {
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log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
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RTLIL::Wire *new_wire = NULL;
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if (!portname2.empty()) {
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new_wire = new RTLIL::Wire;
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*new_wire = *wire;
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wire->name = NEW_ID;
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module->wires[wire->name] = wire;
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module->wires[new_wire->name] = new_wire;
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}
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if (!portname2.empty())
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new_wire = module->addWire(NEW_ID, wire);
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if (flag_bits)
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{
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@ -128,14 +128,14 @@ struct TechmapWorker
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for (auto &it : tpl->wires) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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apply_prefix(cell->name, w->name);
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std::string w_name = it.second->name;
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apply_prefix(cell->name, w_name);
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RTLIL::Wire *w = module->addWire(w_name, it.second);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute("\\_techmap_special_"))
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w->attributes.clear();
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module->add(w);
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design->select(module, w);
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}
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@ -381,7 +381,6 @@ struct TechmapWorker
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
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techmap_wire_names.erase(it.first);
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tpl->wires.erase(data.wire->name);
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const char *p = data.wire->name.c_str();
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const char *q = strrchr(p+1, '.');
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@ -391,8 +390,7 @@ struct TechmapWorker
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std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
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while (tpl->wires.count(new_name))
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new_name += "_";
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data.wire->name = new_name;
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tpl->add(data.wire);
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tpl->rename(data.wire, new_name);
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std::string cmd_string = data.value.as_const().decode_string();
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Pass::call_on_module(map, tpl, cmd_string);
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