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Added new cell types to manual

This commit is contained in:
Clifford Wolf 2013-12-28 12:10:32 +01:00
parent c69c416d28
commit fe8ec32a1c
2 changed files with 10 additions and 1 deletions
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9
manual/CHAPTER_CellLib.tex
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@ -97,6 +97,12 @@ The width of the output port \B{Y}.
Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always
extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments
with {\tt x}-bits if the most significant bit is {\tt x}.) This is used
internally to correctly implement the {\tt ==} and {\tt !=} operators for
constant arguments.
\subsection{Multiplexers}
Multiplexers are generated by the Verilog HDL frontend for {\tt
@ -147,6 +153,9 @@ Verilog & Cell Type \\
\hline
\lstinline[language=Verilog]; Y = A && B; & {\tt \$logic\_and} \\
\lstinline[language=Verilog]; Y = A || B; & {\tt \$logic\_or} \\
\hline
\lstinline[language=Verilog]; Y = A === B; & {\tt \$eqx} \\
\lstinline[language=Verilog]; Y = A !== B; & {\tt \$nex} \\
\end{tabular}
\hfil
\begin{tabular}[t]{ll}

2
passes/techmap/simplemap.cc
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@ -498,7 +498,7 @@ struct SimplemapPass : public Pass {
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
log("primitives. The following internal cell types are mapped by this pass:\n");
log("\n");
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $not, $pos, $bu0, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
log(" $logic_not, $logic_and, $logic_or, $mux\n");
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");