mirror of https://github.com/YosysHQ/yosys.git
If init is 1'bx, do not add to dict as per @cliffordwolf
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@ -102,7 +102,8 @@ struct DffinitPass : public Pass {
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if (wire->attributes.count("\\init")) {
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Const value = wire->attributes.at("\\init");
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for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
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init_bits[sigmap(SigBit(wire, i))] = value[i];
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if (value[i] != State::Sx)
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init_bits[sigmap(SigBit(wire, i))] = value[i];
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}
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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