mirror of https://github.com/YosysHQ/yosys.git
Complete rewrite of pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
1bf8c2b823
commit
481f0015be
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@ -45,35 +45,273 @@ struct Pmux2ShiftxPass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells())
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{
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if (cell->type != "$pmux")
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continue;
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SigMap sigmap(module);
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// Create a new encoder, out of a $pmux, that takes
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// the existing pmux's 'S' input and transforms it
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// back into a binary value
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RTLIL::SigSpec shiftx_a;
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RTLIL::SigSpec pmux_s;
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dict<SigBit, pair<SigSpec, Const>> eqdb;
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int s_width = cell->getParam("\\S_WIDTH").as_int();
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if (!cell->getPort("\\A").is_fully_undef()) {
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++s_width;
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shiftx_a.append(cell->getPort("\\A"));
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pmux_s.append(module->Not(NEW_ID, module->ReduceOr(NEW_ID, cell->getPort("\\S"))));
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$eq")
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{
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dict<SigBit, State> bits;
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SigSpec A = sigmap(cell->getPort("\\A"));
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SigSpec B = sigmap(cell->getPort("\\B"));
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if (a_width < b_width) {
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bool a_signed = cell->getParam("\\A_SIGNED").as_int();
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A.extend_u0(b_width, a_signed);
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}
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if (b_width < a_width) {
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bool b_signed = cell->getParam("\\B_SIGNED").as_int();
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B.extend_u0(a_width, b_signed);
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}
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for (int i = 0; i < GetSize(A); i++) {
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SigBit a_bit = A[i], b_bit = B[i];
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if (b_bit.wire && !a_bit.wire) {
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std::swap(a_bit, b_bit);
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}
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if (!a_bit.wire || b_bit.wire)
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goto next_cell;
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if (bits.count(a_bit))
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goto next_cell;
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bits[a_bit] = b_bit.data;
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}
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if (GetSize(bits) > 20)
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goto next_cell;
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bits.sort();
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pair<SigSpec, Const> entry;
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for (auto it : bits) {
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entry.first.append_bit(it.first);
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entry.second.bits.push_back(it.second);
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}
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eqdb[sigmap(cell->getPort("\\Y")[0])] = entry;
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goto next_cell;
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}
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if (cell->type == "$logic_not")
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{
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dict<SigBit, State> bits;
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SigSpec A = sigmap(cell->getPort("\\A"));
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for (int i = 0; i < GetSize(A); i++)
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bits[A[i]] = State::S0;
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bits.sort();
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pair<SigSpec, Const> entry;
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for (auto it : bits) {
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entry.first.append_bit(it.first);
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entry.second.bits.push_back(it.second);
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}
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eqdb[sigmap(cell->getPort("\\Y")[0])] = entry;
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goto next_cell;
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}
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next_cell:;
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}
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const int clog2width = ceil(log2(s_width));
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RTLIL::SigSpec pmux_b;
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for (int i = s_width-1; i >= 0; i--)
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pmux_b.append(RTLIL::Const(i, clog2width));
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shiftx_a.append(cell->getPort("\\B"));
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pmux_s.append(cell->getPort("\\S"));
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for (auto cell : module->selected_cells())
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{
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if (cell->type != "$pmux")
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continue;
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RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width);
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module->addPmux(NEW_ID, RTLIL::Const(RTLIL::Sx, clog2width), pmux_b, pmux_s, pmux_y);
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module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y"));
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module->remove(cell);
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string src = cell->get_src_attribute();
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int width = cell->getParam("\\WIDTH").as_int();
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int width_bits = ceil_log2(width);
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int extwidth = width;
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while (extwidth & (extwidth-1))
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extwidth++;
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dict<SigSpec, pool<int>> seldb;
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SigSpec S = sigmap(cell->getPort("\\S"));
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for (int i = 0; i < GetSize(S); i++)
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{
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if (!eqdb.count(S[i]))
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continue;
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auto &entry = eqdb.at(S[i]);
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seldb[entry.first].insert(i);
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}
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if (seldb.empty())
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continue;
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log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
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log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
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SigSpec updated_S = cell->getPort("\\S");
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SigSpec updated_B = cell->getPort("\\B");
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#if 1
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for (auto &it : seldb) {
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string msg = stringf("seldb: %s ->", log_signal(it.first));
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for (int i : it.second)
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msg += stringf(" %d(%s)", i, log_signal(eqdb.at(S[i]).second));
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log(" %s\n", msg.c_str());
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}
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#endif
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while (!seldb.empty())
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{
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// pick the largest entry in seldb
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SigSpec sig = seldb.begin()->first;
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for (auto &it : seldb) {
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if (GetSize(sig) < GetSize(it.first))
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sig = it.first;
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else if (GetSize(seldb.at(sig)) < GetSize(it.second))
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sig = it.first;
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}
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log(" checking ctrl signal %s\n", log_signal(sig));
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// find the relevant choices
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dict<Const, int> choices;
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vector<int> onescnt(GetSize(sig));
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for (int i : seldb.at(sig)) {
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Const val = eqdb.at(S[i]).second;
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choices[val] = i;
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for (int k = 0; k < GetSize(val); k++)
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if (val[k] == State::S1)
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onescnt[k] |= 1;
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else
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onescnt[k] |= 2;
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}
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// TBD: also find choices that are using signals that are subsets of the bits in "sig"
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// find the best permutation
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vector<pair<int, int>> perm(GetSize(sig));
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for (int i = 0; i < GetSize(onescnt); i++)
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perm[i] = make_pair(onescnt[i], i);
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// TBD: this is not the best permutation
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std::sort(perm.rbegin(), perm.rend());
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// permutated sig
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Const perm_xormask(State::S0, GetSize(sig));
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SigSpec perm_sig(State::S0, GetSize(sig));
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for (int i = 0; i < GetSize(sig); i++) {
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if (perm[i].first == 1)
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perm_xormask[i] = State::S1;
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perm_sig[i] = sig[perm[i].second];
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}
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log(" best permutation: %s\n", log_signal(perm_sig));
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log(" best xor mask: %s\n", log_signal(perm_xormask));
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// permutated choices
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int min_choice = 1 << 30;
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int max_choice = -1;
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dict<Const, int> perm_choices;
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for (auto &it : choices)
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{
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Const &old_c = it.first;
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Const new_c(State::S0, GetSize(old_c));
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for (int i = 0; i < GetSize(old_c); i++)
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new_c[i] = old_c[perm[i].second];
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Const new_c_before_xor = new_c;
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new_c = const_xor(new_c, perm_xormask, false, false, GetSize(new_c));
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perm_choices[new_c] = it.second;
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min_choice = std::min(min_choice, new_c.as_int());
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max_choice = std::max(max_choice, new_c.as_int());
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log(" %s -> %s -> %s\n", log_signal(old_c), log_signal(new_c_before_xor), log_signal(new_c));
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}
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log(" choices: %d\n", GetSize(choices));
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log(" min choice: %d\n", min_choice);
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log(" max choice: %d\n", max_choice);
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log(" range density: %d%%\n", 100*GetSize(choices)/(max_choice-min_choice+1));
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log(" absolute density: %d%%\n", 100*GetSize(choices)/(max_choice+1));
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bool full_case = (min_choice == 0) && (max_choice == (1 << GetSize(sig))-1) && (max_choice+1 == GetSize(choices));
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log(" full case: %s\n", full_case ? "true" : "false");
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// use arithmetic offset if density is less than 30%
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Const offset(State::S0, GetSize(sig));
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if (3*GetSize(choices) < max_choice && 3*GetSize(choices) >= (max_choice-min_choice))
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{
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log(" using offset method.\n");
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offset = Const(min_choice, GetSize(sig));
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min_choice -= offset.as_int();
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max_choice -= offset.as_int();
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dict<Const, int> new_perm_choices;
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for (auto &it : perm_choices)
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new_perm_choices[const_sub(it.first, offset, false, false, GetSize(sig))] = it.second;
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perm_choices.swap(new_perm_choices);
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}
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// ignore cases with a absolute density of less than 30%
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if (3*GetSize(choices) < max_choice) {
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log(" insufficient density.\n");
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seldb.erase(sig);
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continue;
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}
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// creat cmp signal
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SigSpec cmp = perm_sig;
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if (perm_xormask.as_bool())
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cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src);
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if (offset.as_bool())
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cmp = module->Sub(NEW_ID, cmp, offset, false, src);
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// create enable signal
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SigBit en = State::S1;
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if (!full_case) {
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Const enable_mask(State::S0, max_choice+1);
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for (auto &it : perm_choices)
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enable_mask[it.first.as_int()] = State::S1;
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en = module->addWire(NEW_ID);
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module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
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}
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// create data signal
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SigSpec data(State::Sx, (max_choice+1)*extwidth);
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for (auto &it : perm_choices) {
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int position = it.first.as_int()*extwidth;
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int data_index = it.second;
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data.replace(position, cell->getPort("\\B").extract(data_index*width, width));
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updated_S[data_index] = State::S0;
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updated_B.replace(data_index*width, SigSpec(State::Sx, width));
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}
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// create shiftx cell
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SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
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SigSpec outsig = module->addWire(NEW_ID, width);
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Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
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updated_S.append(en);
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updated_B.append(outsig);
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log(" created $shiftx cell %s.\n", log_id(c));
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// remove this sig and continue with the next block
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seldb.erase(sig);
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}
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// update $pmux cell
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cell->setPort("\\S", updated_S);
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cell->setPort("\\B", updated_B);
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cell->setParam("\\S_WIDTH", GetSize(updated_S));
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}
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}
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}
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} Pmux2ShiftxPass;
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