mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/master' into xc7srl
This commit is contained in:
Eddie Hung
commit
46753cf89f
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@ -45,7 +45,7 @@ namespace AST {
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// instantiate global variables (private API)
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namespace AST_INTERNAL {
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bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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AstNode *current_ast, *current_ast_mod;
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std::map<std::string, AstNode*> current_scope;
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@ -431,9 +431,12 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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break;
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case AST_RANGE:
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if (range_valid)
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fprintf(f, "[%d:%d]", range_left, range_right);
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else {
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if (range_valid) {
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if (range_swapped)
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fprintf(f, "[%d:%d]", range_right, range_left);
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else
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fprintf(f, "[%d:%d]", range_left, range_right);
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} else {
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for (auto child : children) {
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fprintf(f, "%c", first ? '[' : ':');
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child->dumpVlog(f, "");
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@ -562,7 +565,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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case AST_CONCAT:
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fprintf(f, "{");
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for (auto child : children) {
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for (int i = GetSize(children)-1; i >= 0; i--) {
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auto child = children[i];
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if (!first)
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fprintf(f, ", ");
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child->dumpVlog(f, "");
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@ -926,23 +930,28 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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ast_before_simplify = ast->clone();
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if (flag_dump_ast1) {
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log("Dumping Verilog AST before simplification:\n");
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log("Dumping AST before simplification:\n");
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ast->dumpAst(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (flag_dump_vlog1) {
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log("Dumping Verilog AST before simplification:\n");
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ast->dumpVlog(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (!defer)
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{
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while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
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if (flag_dump_ast2) {
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log("Dumping Verilog AST after simplification:\n");
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log("Dumping AST after simplification:\n");
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ast->dumpAst(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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if (flag_dump_vlog) {
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log("Dumping Verilog AST (as requested by dump_vlog option):\n");
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if (flag_dump_vlog2) {
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log("Dumping Verilog AST after simplification:\n");
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ast->dumpVlog(NULL, " ");
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log("--- END OF AST DUMP ---\n");
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}
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@ -1016,14 +1025,15 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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}
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// create AstModule instances for all modules in the AST tree and add them to 'design'
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
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void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
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{
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current_ast = ast;
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flag_dump_ast1 = dump_ast1;
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flag_dump_ast2 = dump_ast2;
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flag_no_dump_ptr = no_dump_ptr;
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flag_dump_vlog = dump_vlog;
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flag_dump_vlog1 = dump_vlog1;
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flag_dump_vlog2 = dump_vlog2;
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flag_dump_rtlil = dump_rtlil;
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flag_nolatches = nolatches;
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flag_nomeminit = nomeminit;
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@ -1357,7 +1367,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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current_ast = NULL;
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flag_dump_ast1 = false;
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flag_dump_ast2 = false;
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flag_dump_vlog = false;
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flag_dump_vlog1 = false;
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flag_dump_vlog2 = false;
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flag_nolatches = nolatches;
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flag_nomeminit = nomeminit;
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flag_nomem2reg = nomem2reg;
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@ -282,7 +282,7 @@ namespace AST
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};
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
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bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
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// parametric modules are supported directly by the AST library
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|
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@ -138,9 +138,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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int mem_width, mem_size, addr_bits;
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node->meminfo(mem_width, mem_size, addr_bits);
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int data_range_left = node->children[0]->range_left;
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int data_range_right = node->children[0]->range_right;
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if (node->children[0]->range_swapped)
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std::swap(data_range_left, data_range_right);
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for (int i = 0; i < mem_size; i++) {
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AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
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mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
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reg->str = stringf("%s[%d]", node->str.c_str(), i);
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reg->is_reg = true;
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reg->is_signed = node->is_signed;
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@ -976,6 +982,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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int data_range_left = id2ast->children[0]->range_left;
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int data_range_right = id2ast->children[0]->range_right;
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if (id2ast->children[0]->range_swapped)
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std::swap(data_range_left, data_range_right);
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std::stringstream sstr;
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sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
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std::string wire_id = sstr.str();
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@ -81,6 +81,9 @@ struct VerilogFrontend : public Frontend {
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log(" -assert-assumes\n");
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log(" treat all assume() statements like assert() statements\n");
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log("\n");
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log(" -debug\n");
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log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
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log("\n");
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log(" -dump_ast1\n");
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log(" dump abstract syntax tree (before simplification)\n");
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log("\n");
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@ -90,7 +93,10 @@ struct VerilogFrontend : public Frontend {
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log(" -no_dump_ptr\n");
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log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" -dump_vlog1\n");
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log(" dump ast as Verilog code (before simplification)\n");
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log("\n");
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log(" -dump_vlog2\n");
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log(" dump ast as Verilog code (after simplification)\n");
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log("\n");
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log(" -dump_rtlil\n");
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@ -197,7 +203,8 @@ struct VerilogFrontend : public Frontend {
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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bool flag_no_dump_ptr = false;
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bool flag_dump_vlog = false;
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bool flag_dump_vlog1 = false;
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bool flag_dump_vlog2 = false;
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bool flag_dump_rtlil = false;
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bool flag_nolatches = false;
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bool flag_nomeminit = false;
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@ -258,6 +265,14 @@ struct VerilogFrontend : public Frontend {
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assert_assumes_mode = true;
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continue;
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}
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if (arg == "-debug") {
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flag_dump_ast1 = true;
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flag_dump_ast2 = true;
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flag_dump_vlog1 = true;
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flag_dump_vlog2 = true;
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frontend_verilog_yydebug = true;
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continue;
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}
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if (arg == "-dump_ast1") {
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flag_dump_ast1 = true;
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continue;
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@ -270,8 +285,12 @@ struct VerilogFrontend : public Frontend {
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flag_no_dump_ptr = true;
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continue;
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}
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if (arg == "-dump_vlog") {
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flag_dump_vlog = true;
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if (arg == "-dump_vlog1") {
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flag_dump_vlog1 = true;
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continue;
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}
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if (arg == "-dump_vlog2") {
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flag_dump_vlog2 = true;
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continue;
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}
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if (arg == "-dump_rtlil") {
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@ -410,7 +429,7 @@ struct VerilogFrontend : public Frontend {
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if (flag_nodpi)
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error_on_dpi_function(current_ast);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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delete lexin;
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@ -54,6 +54,7 @@ struct WreduceWorker
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std::set<SigBit> work_queue_bits;
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pool<SigBit> keep_bits;
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dict<SigBit, State> init_bits;
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pool<SigBit> remove_init_bits;
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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@ -164,6 +165,7 @@ struct WreduceWorker
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{
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if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
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module->connect(sig_q[i], State::S0);
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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sig_q.remove(i);
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continue;
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@ -171,6 +173,7 @@ struct WreduceWorker
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|
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if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
|
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module->connect(sig_q[i], sig_q[i-1]);
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remove_init_bits.insert(sig_q[i]);
|
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sig_d.remove(i);
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sig_q.remove(i);
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continue;
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@ -178,6 +181,7 @@ struct WreduceWorker
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auto info = mi.query(sig_q[i]);
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if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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sig_q.remove(i);
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zero_ext = false;
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|
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@ -387,13 +391,16 @@ struct WreduceWorker
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|
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void run()
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{
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// create a copy as mi.sigmap will be updated as we process the module
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SigMap init_attr_sigmap = mi.sigmap;
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|
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for (auto w : module->wires()) {
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if (w->get_bool_attribute("\\keep"))
|
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for (auto bit : mi.sigmap(w))
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keep_bits.insert(bit);
|
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if (w->attributes.count("\\init")) {
|
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Const initval = w->attributes.at("\\init");
|
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SigSpec initsig = mi.sigmap(w);
|
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SigSpec initsig = init_attr_sigmap(w);
|
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int width = std::min(GetSize(initval), GetSize(initsig));
|
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for (int i = 0; i < width; i++)
|
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init_bits[initsig[i]] = initval[i];
|
||||
|
|
@ -446,6 +453,24 @@ struct WreduceWorker
|
|||
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
|
||||
module->swap_names(w, nw);
|
||||
}
|
||||
|
||||
if (!remove_init_bits.empty()) {
|
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for (auto w : module->wires()) {
|
||||
if (w->attributes.count("\\init")) {
|
||||
Const initval = w->attributes.at("\\init");
|
||||
Const new_initval(State::Sx, GetSize(w));
|
||||
SigSpec initsig = init_attr_sigmap(w);
|
||||
int width = std::min(GetSize(initval), GetSize(initsig));
|
||||
for (int i = 0; i < width; i++) {
|
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log_dump(initsig[i], remove_init_bits.count(initsig[i]));
|
||||
if (!remove_init_bits.count(initsig[i]))
|
||||
new_initval[i] = initval[i];
|
||||
}
|
||||
w->attributes.at("\\init") = new_initval;
|
||||
log_dump(w->name, initval, new_initval);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ function xtract_cell_decl()
|
|||
{
|
||||
for dir in $libdir/xeclib $libdir/retarget; do
|
||||
[ -f $dir/$1.v ] || continue
|
||||
[ -z "$2" ] || echo $2
|
||||
egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
|
||||
sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
|
||||
s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
|
||||
|
|
@ -37,10 +38,10 @@ function xtract_cell_decl()
|
|||
xtract_cell_decl BUFMR
|
||||
xtract_cell_decl BUFMRCE
|
||||
xtract_cell_decl BUFR
|
||||
xtract_cell_decl CAPTUREE2
|
||||
xtract_cell_decl CAPTUREE2 "(* keep *)"
|
||||
# xtract_cell_decl CARRY4
|
||||
xtract_cell_decl CFGLUT5
|
||||
xtract_cell_decl DCIRESET
|
||||
xtract_cell_decl DCIRESET "(* keep *)"
|
||||
xtract_cell_decl DNA_PORT
|
||||
xtract_cell_decl DSP48E1
|
||||
xtract_cell_decl EFUSE_USR
|
||||
|
|
@ -67,10 +68,10 @@ function xtract_cell_decl()
|
|||
xtract_cell_decl IBUFDS_GTE2
|
||||
xtract_cell_decl IBUFDS_IBUFDISABLE
|
||||
xtract_cell_decl IBUFDS_INTERMDISABLE
|
||||
xtract_cell_decl ICAPE2
|
||||
xtract_cell_decl ICAPE2 "(* keep *)"
|
||||
xtract_cell_decl IDDR
|
||||
xtract_cell_decl IDDR_2CLK
|
||||
xtract_cell_decl IDELAYCTRL
|
||||
xtract_cell_decl IDELAYCTRL "(* keep *)"
|
||||
xtract_cell_decl IDELAYE2
|
||||
xtract_cell_decl IN_FIFO
|
||||
xtract_cell_decl IOBUF
|
||||
|
|
@ -112,7 +113,7 @@ function xtract_cell_decl()
|
|||
xtract_cell_decl PHY_CONTROL
|
||||
xtract_cell_decl PLLE2_ADV
|
||||
xtract_cell_decl PLLE2_BASE
|
||||
xtract_cell_decl PS7
|
||||
xtract_cell_decl PS7 "(* keep *)"
|
||||
xtract_cell_decl PULLDOWN
|
||||
xtract_cell_decl PULLUP
|
||||
xtract_cell_decl RAM128X1D
|
||||
|
|
@ -137,6 +138,7 @@ function xtract_cell_decl()
|
|||
#xtract_cell_decl SRL16E
|
||||
#xtract_cell_decl SRLC32E
|
||||
xtract_cell_decl STARTUPE2
|
||||
xtract_cell_decl STARTUPE2 "(* keep *)"
|
||||
xtract_cell_decl USR_ACCESSE2
|
||||
xtract_cell_decl XADC
|
||||
} > cells_xtra.new
|
||||
|
|
|
|||
|
|
@ -114,6 +114,7 @@ module BUFR (...);
|
|||
parameter SIM_DEVICE = "7SERIES";
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module CAPTUREE2 (...);
|
||||
parameter ONESHOT = "TRUE";
|
||||
input CAP;
|
||||
|
|
@ -130,6 +131,7 @@ module CFGLUT5 (...);
|
|||
input CDI, CE, CLK;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module DCIRESET (...);
|
||||
output LOCKED;
|
||||
input RST;
|
||||
|
|
@ -2102,6 +2104,7 @@ module IBUFDS_INTERMDISABLE (...);
|
|||
input INTERMDISABLE;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module ICAPE2 (...);
|
||||
parameter [31:0] DEVICE_ID = 32'h04244093;
|
||||
parameter ICAP_WIDTH = "X32";
|
||||
|
|
@ -2149,6 +2152,7 @@ module IDDR_2CLK (...);
|
|||
input S;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module IDELAYCTRL (...);
|
||||
parameter SIM_DEVICE = "7SERIES";
|
||||
output RDY;
|
||||
|
|
@ -3057,6 +3061,7 @@ module PLLE2_BASE (...);
|
|||
input RST;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module PS7 (...);
|
||||
output DMA0DAVALID;
|
||||
output DMA0DRREADY;
|
||||
|
|
@ -3688,6 +3693,17 @@ module PULLUP (...);
|
|||
output O;
|
||||
endmodule
|
||||
|
||||
module RAM128X1D (...);
|
||||
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
output DPO, SPO;
|
||||
input [6:0] A;
|
||||
input [6:0] DPRA;
|
||||
input D;
|
||||
input WCLK;
|
||||
input WE;
|
||||
endmodule
|
||||
|
||||
module RAM128X1S (...);
|
||||
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -3695,25 +3711,6 @@ module RAM128X1S (...);
|
|||
input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
input [6:0] A, DPRA
|
||||
);
|
||||
parameter [127:0] INIT = 128'bx;
|
||||
parameter IS_WCLK_INVERTED = 0;
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter [63:0] INIT = 64'bx;
|
||||
parameter IS_WCLK_INVERTED = 0;
|
||||
endmodule
|
||||
|
||||
module RAM256X1S (...);
|
||||
parameter [255:0] INIT = 256'h0;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -3797,6 +3794,13 @@ module RAM64M (...);
|
|||
input WE;
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
output DPO, SPO;
|
||||
input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
module RAM64X1S (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -3843,6 +3847,7 @@ module ROM64X1 (...);
|
|||
input A0, A1, A2, A3, A4, A5;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module STARTUPE2 (...);
|
||||
parameter PROG_USR = "FALSE";
|
||||
parameter real SIM_CCLK_FREQ = 0.0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue