mirror of https://github.com/YosysHQ/yosys.git
Add '-nosrl' option to synth_xilinx
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@ -64,10 +64,13 @@ struct SynthXilinxPass : public Pass
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -nobram\n");
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log(" disable infering of block rams\n");
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log(" disable inference of block rams\n");
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log("\n");
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log(" -nodram\n");
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log(" disable infering of distributed rams\n");
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log(" disable inference of distributed rams\n");
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log("\n");
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log(" -nobram\n");
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log(" disable inference of shift registers\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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@ -110,8 +113,8 @@ struct SynthXilinxPass : public Pass
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log(" dffsr2dff\n");
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log(" dff2dffe\n");
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log(" opt -full\n");
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log(" simplemap t:$dff*\n");
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log(" shregmap -tech xilinx\n");
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log(" simplemap t:$dff* (only without -nosrl)\n");
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log(" shregmap -tech xilinx (only without -nosrl)\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
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log(" opt -fast\n");
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log("\n");
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@ -149,6 +152,7 @@ struct SynthXilinxPass : public Pass
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bool vpr = false;
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bool nobram = false;
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bool nodram = false;
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bool nosrl = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -193,6 +197,10 @@ struct SynthXilinxPass : public Pass
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nodram = true;
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continue;
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}
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if (args[argidx] == "-nosrl") {
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nosrl = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -257,8 +265,10 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "dff2dffe");
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Pass::call(design, "opt -full");
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Pass::call(design, "simplemap t:$dff*");
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Pass::call(design, "shregmap -tech xilinx");
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if (!nosrl) {
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Pass::call(design, "simplemap t:$dff*");
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Pass::call(design, "shregmap -tech xilinx");
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}
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if (vpr) {
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
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