mirror of https://github.com/YosysHQ/yosys.git
Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr
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@ -1252,6 +1252,78 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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// remove redundant pairs of bits in ==, ===, !=, and !==
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// replace cell with const driver if inputs can't be equal
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if (do_fine && cell->type.in("$eq", "$ne", "$eqx", "$nex"))
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{
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pool<pair<SigBit, SigBit>> redundant_cache;
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mfp<SigBit> contradiction_cache;
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contradiction_cache.promote(State::S0);
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contradiction_cache.promote(State::S1);
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width);
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SigSpec sig_a = cell->getPort("\\A");
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SigSpec sig_b = cell->getPort("\\B");
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int redundant_bits = 0;
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for (int i = width-1; i >= 0; i--)
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{
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SigBit bit_a = i < a_width ? assign_map(sig_a[i]) : State::S0;
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SigBit bit_b = i < b_width ? assign_map(sig_b[i]) : State::S0;
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contradiction_cache.merge(bit_a, bit_b);
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if (bit_b < bit_a)
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std::swap(bit_a, bit_b);
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pair<SigBit, SigBit> key(bit_a, bit_b);
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if (redundant_cache.count(key)) {
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if (i < a_width) sig_a.remove(i);
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if (i < b_width) sig_b.remove(i);
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redundant_bits++;
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continue;
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}
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redundant_cache.insert(key);
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}
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if (contradiction_cache.find(State::S0) == contradiction_cache.find(State::S1))
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{
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SigSpec y_sig = cell->getPort("\\Y");
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Const y_value(cell->type.in("$eq", "$eqx") ? 0 : 1, GetSize(y_sig));
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log("Replacing cell `%s' in module `%s' with constant driver %s.\n",
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log_id(cell), log_id(module), log_signal(y_value));
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module->connect(y_sig, y_value);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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if (redundant_bits)
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{
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log("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
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redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
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cell->setPort("\\A", sig_a);
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cell->setPort("\\B", sig_b);
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cell->setParam("\\A_WIDTH", GetSize(sig_a));
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cell->setParam("\\B_WIDTH", GetSize(sig_b));
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did_something = true;
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goto next_cell;
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}
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}
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// replace a<0 or a>=0 with the top bit of a
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if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
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{
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