mirror of https://github.com/YosysHQ/yosys.git
Added "wreduce -memx"
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15ef608453
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@ -366,15 +366,26 @@ struct WreducePass : public Pass {
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log(" assign y = a + b + c + 1;\n");
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log(" endmodule\n");
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log("\n");
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log("Options:\n");
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log("\n");
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log(" -memx\n");
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log(" Do not change the width of memory address ports. Use this options in\n");
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log(" flows that use the 'memory_memx' pass.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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WreduceConfig config;
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bool opt_memx = false;
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log_header(design, "Executing WREDUCE pass (reducing word size of cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-memx") {
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opt_memx = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -397,12 +408,12 @@ struct WreducePass : public Pass {
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module->connect(sig, Const(0, GetSize(sig)));
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}
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}
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if (c->type.in("$memrd", "$memwr", "$meminit")) {
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if (!opt_memx && c->type.in("$memrd", "$memwr", "$meminit")) {
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IdString memid = c->getParam("\\MEMID").decode_string();
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RTLIL::Memory *mem = module->memories.at(memid);
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if (mem->start_offset == 0) {
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if (mem->start_offset >= 0) {
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int cur_addrbits = c->getParam("\\ABITS").as_int();
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int max_addrbits = ceil_log2(mem->size);
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int max_addrbits = ceil_log2(mem->start_offset + mem->size);
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if (cur_addrbits > max_addrbits) {
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log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
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cur_addrbits-max_addrbits, cur_addrbits,
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@ -173,8 +173,12 @@ struct PrepPass : public ScriptPass
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run("opt_clean");
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run("check");
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run("opt -keepdc");
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if (!ifxmode)
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run("wreduce");
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if (!ifxmode) {
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if (help_mode)
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run("wreduce [-memx]");
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else
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run(memxmode ? "wreduce -memx" : "wreduce");
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}
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run("memory_dff" + (help_mode ? " [-nordff]" : memory_opts));
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if (help_mode || memxmode)
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run("memory_memx", "(if -memx)");
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