mirror of https://github.com/YosysHQ/yosys.git
Bugfixes for empty signal vectors
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@ -217,6 +217,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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assign_map.apply(a); \
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if (a.is_fully_const()) { \
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a.optimize(); \
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if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \
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RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
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RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, dummy_arg, \
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cell->parameters["\\A_SIGNED"].as_bool(), false, \
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@ -232,6 +233,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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assign_map.apply(a), assign_map.apply(b); \
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if (a.is_fully_const() && b.is_fully_const()) { \
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a.optimize(), b.optimize(); \
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if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \
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if (b.chunks.empty()) b.chunks.push_back(RTLIL::SigChunk()); \
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RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, b.chunks[0].data, \
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cell->parameters["\\A_SIGNED"].as_bool(), \
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cell->parameters["\\B_SIGNED"].as_bool(), \
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