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Fixed sign propagation in bit-wise operators

This commit is contained in:
Clifford Wolf 2013-07-09 23:53:55 +02:00
parent 5dab327b30
commit ed62fcdbe2
1 changed files with 1 additions and 0 deletions
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frontends/ast/genrtlil.cc
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@ -896,6 +896,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = std::max(left.width, right.width);
if (width_hint > 0)
width = width_hint;
is_signed = children[0]->is_signed && children[1]->is_signed;
return binop2rtlil(this, type_name, width, left, right);
}