mirror of https://github.com/YosysHQ/yosys.git
opt_lut: collect and display statistics.
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@ -30,6 +30,11 @@ struct OptLutWorker
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ModIndex index;
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SigMap sigmap;
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pool<RTLIL::Cell*> luts;
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dict<RTLIL::Cell*, int> luts_arity;
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int combined_count = 0;
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bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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{
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SigSpec lut_input = sigmap(lut->getPort("\\A"));
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@ -53,12 +58,27 @@ struct OptLutWorker
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return lut_table.extract(lut_index).as_int();
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}
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void show_stats_by_arity()
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{
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dict<int, int> arity_counts;
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int max_arity = 0;
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for (auto lut_arity : luts_arity)
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{
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max_arity = max(max_arity, lut_arity.second);
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arity_counts[lut_arity.second]++;
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}
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log("Number of LUTs: %6zu\n", luts.size());
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for (int arity = 1; arity <= max_arity; arity++)
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{
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if (arity_counts[arity])
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log(" %d-LUT: %13d\n", arity, arity_counts[arity]);
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}
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}
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OptLutWorker(RTLIL::Module *module) :
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module(module), index(module), sigmap(module)
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{
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pool<RTLIL::Cell*> luts;
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dict<RTLIL::Cell*, int> luts_arity;
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log("Discovering LUTs.\n");
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for (auto cell : module->selected_cells())
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{
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@ -79,10 +99,10 @@ struct OptLutWorker
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luts_arity[cell] = lut_arity;
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}
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}
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show_stats_by_arity();
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log("\n");
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log("Combining LUTs.\n");
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pool<RTLIL::Cell*> worklist = luts;
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while (worklist.size())
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{
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@ -241,9 +261,12 @@ struct OptLutWorker
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worklist.insert(lutM);
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worklist.erase(lutR);
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combined_count++;
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}
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}
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}
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show_stats_by_arity();
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}
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};
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@ -271,10 +294,16 @@ struct OptLutPass : public Pass {
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules())
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{
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OptLutWorker worker(module);
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total_count += worker.combined_count;
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("\n");
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log("Combined %d LUTs.\n", total_count);
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}
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} OptLutPass;
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