mirror of https://github.com/YosysHQ/yosys.git
Added SigPool::check(bit)
This commit is contained in:
parent
ddd31a0b66
commit
0c86d6106c
|
@ -93,6 +93,11 @@ struct SigPool
|
|||
return result;
|
||||
}
|
||||
|
||||
bool check(RTLIL::SigBit bit)
|
||||
{
|
||||
return bit.wire != NULL && bits.count(bit);
|
||||
}
|
||||
|
||||
bool check_any(RTLIL::SigSpec sig)
|
||||
{
|
||||
for (auto &bit : sig)
|
||||
|
|
|
@ -251,10 +251,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
|
|||
for (int i = 0; i < SIZE(sig); i++) {
|
||||
if (sig[i].wire == NULL)
|
||||
continue;
|
||||
if (!used_signals_nodrivers.check_any(sig[i])) {
|
||||
if (!used_signals_nodrivers.check(sig[i])) {
|
||||
if (!unused_bits.empty())
|
||||
unused_bits += " ";
|
||||
unused_bits += stringf("%zd", i);
|
||||
unused_bits += stringf("%d", i);
|
||||
}
|
||||
}
|
||||
if (unused_bits.empty() || wire->port_id != 0)
|
||||
|
|
Loading…
Reference in New Issue