mirror of https://github.com/YosysHQ/yosys.git
Started to implement real resource sharing
This commit is contained in:
Clifford Wolf
parent
02f0acb3bc
commit
2278995bd8
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@ -4,4 +4,5 @@ OBJS += passes/sat/freduce.o
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OBJS += passes/sat/eval.o
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OBJS += passes/sat/miter.o
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OBJS += passes/sat/expose.o
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OBJS += passes/sat/share.o
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@ -0,0 +1,443 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include "kernel/modwalker.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <algorithm>
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struct ShareWorkerConfig
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{
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bool opt_all;
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};
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struct ShareWorker
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{
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ShareWorkerConfig config;
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RTLIL::Design *design;
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RTLIL::Module *module;
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CellTypes cone_ct;
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ModWalker modwalker;
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// ---------------------------------------------------
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// Find shareable cells and compatible groups of cells
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// ---------------------------------------------------
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std::set<RTLIL::Cell*> shareable_cells;
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void find_shareable_cells()
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{
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std::vector<RTLIL::Cell*> candidates;
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for (auto &it : module->cells)
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{
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RTLIL::Cell *cell = it.second;
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if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
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continue;
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if (config.opt_all) {
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candidates.push_back(cell);
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continue;
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}
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if (cell->type == "$memrd") {
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if (!cell->parameters.at("\\CLK_ENABLE").as_bool())
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candidates.push_back(cell);
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continue;
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}
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if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
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if (cell->parameters.at("\\Y_WIDTH").as_int() > 4)
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candidates.push_back(cell);
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continue;
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}
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if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
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if (cell->parameters.at("\\Y_WIDTH").as_int() > 8)
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candidates.push_back(cell);
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continue;
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}
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}
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for (auto cell : candidates)
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{
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std::set<ModWalker::PortBit> driven_bits;
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modwalker.get_consumers(driven_bits, modwalker.cell_outputs[cell]);
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for (auto bit : driven_bits) {
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if (bit.cell->type != "$mux" && bit.cell->type != "$pmux")
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goto skip_candidate;
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if (bit.port != "\\A" && bit.port != "\\B")
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goto skip_candidate;
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}
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if (!modwalker.has_outputs(modwalker.cell_outputs[cell]))
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shareable_cells.insert(cell);
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skip_candidate:;
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}
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}
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bool is_shareable_pair(RTLIL::Cell *c1, RTLIL::Cell *c2)
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{
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if (c1->type != c2->type)
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return false;
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if (c1->type == "$memrd")
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{
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if (c1->parameters.at("\\MEMID").decode_string() != c2->parameters.at("\\MEMID").decode_string())
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return false;
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return true;
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}
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if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" ||
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c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
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{
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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return false;
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if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
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return false;
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
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if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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return true;
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}
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for (auto &it : c1->parameters)
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if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second)
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return false;
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for (auto &it : c2->parameters)
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if (c1->parameters.count(it.first) == 0 || c1->parameters.at(it.first) != it.second)
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return false;
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return true;
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}
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void find_shareable_partners(std::vector<RTLIL::Cell*> &results, RTLIL::Cell *cell)
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{
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results.clear();
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for (auto c : shareable_cells)
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if (c != cell && is_shareable_pair(c, cell))
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results.push_back(c);
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}
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// --------------------------------------------------------
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// Finding control inputs and activation pattern for a cell
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// --------------------------------------------------------
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std::map<RTLIL::Cell*, std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>>> activation_patterns_cache;
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void follow_mux_data_cone(std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &patterns,
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> &state, RTLIL::SigSpec signal)
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{
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std::set<ModWalker::PortBit> consumers;
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std::map<RTLIL::Cell*, std::set<ModWalker::PortBit>> consumers_by_cell;
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if (modwalker.has_outputs(signal))
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goto signal_outside_mux_tree;
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modwalker.get_consumers(consumers, signal);
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for (auto &bit : consumers) {
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if ((bit.cell->type != "$mux" && bit.cell->type != "$pmux") || bit.port == "\\S")
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goto signal_outside_mux_tree;
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consumers_by_cell[bit.cell].insert(bit);
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}
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if (0) {
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signal_outside_mux_tree:;
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RTLIL::SigSpec pattern_first, pattern_second;
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for (auto &bit : state) {
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pattern_first.append_bit(bit.first);
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pattern_second.append_bit(bit.second);
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}
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patterns.insert(std::pair<RTLIL::SigSpec, RTLIL::Const>(pattern_first, pattern_second.as_const()));
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return;
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}
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for (auto &it : consumers_by_cell)
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{
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RTLIL::Cell *cell = it.first;
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log_assert(cell->type == "$mux" || cell->type == "$pmux");
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int width = cell->parameters.at("\\WIDTH").as_int();
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std::set<int> used_in_b_parts;
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bool used_in_a = false;
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for (auto &bit : it.second) {
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if (bit.port == "\\A")
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used_in_a = true;
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else if (bit.port == "\\B")
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used_in_b_parts.insert(bit.offset / width);
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else
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log_abort();
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}
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std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(cell->connections.at("\\S")).to_sigbit_vector();
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if (used_in_a) {
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> new_state = state;
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for (auto &bit : sig_s) {
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std::pair<RTLIL::SigBit, RTLIL::State> this_state(bit, RTLIL::State::S0);
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std::pair<RTLIL::SigBit, RTLIL::State> this_inv_state(bit, RTLIL::State::S1);
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if (new_state.count(this_inv_state))
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goto conflict_in_a_port;
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new_state.insert(this_state);
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}
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follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y")));
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conflict_in_a_port:;
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}
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for (int part_idx : used_in_b_parts) {
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> new_state = state;
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std::pair<RTLIL::SigBit, RTLIL::State> this_state(sig_s.at(part_idx), RTLIL::State::S1);
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std::pair<RTLIL::SigBit, RTLIL::State> this_inv_state(sig_s.at(part_idx), RTLIL::State::S0);
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if (new_state.count(this_inv_state))
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goto conflict_in_b_port;
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new_state.insert(this_state);
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follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y")));
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conflict_in_b_port:;
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}
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}
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}
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &find_cell_activation_patterns(RTLIL::Cell *cell)
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{
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if (activation_patterns_cache.count(cell))
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return activation_patterns_cache.at(cell);
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> state;
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RTLIL::SigSpec cell_output_signal;
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for (auto &bit : modwalker.cell_outputs[cell])
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cell_output_signal.append_bit(bit);
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follow_mux_data_cone(activation_patterns_cache[cell], state, cell_output_signal);
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return activation_patterns_cache.at(cell);
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}
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RTLIL::SigSpec bits_from_activation_patterns(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns)
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{
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std::set<RTLIL::SigBit> all_bits;
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for (auto &it : activation_patterns) {
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std::vector<RTLIL::SigBit> bits = it.first;
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all_bits.insert(bits.begin(), bits.end());
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}
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RTLIL::SigSpec signal;
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for (auto &bit : all_bits)
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signal.append_bit(bit);
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return signal;
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}
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// -------------
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// Setup and run
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// -------------
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ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
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config(config), design(design), module(module)
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{
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cone_ct.setup_internals();
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cone_ct.cell_types.erase("$mul");
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cone_ct.cell_types.erase("$mod");
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cone_ct.cell_types.erase("$div");
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cone_ct.cell_types.erase("$pow");
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cone_ct.cell_types.erase("$shl");
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cone_ct.cell_types.erase("$shr");
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cone_ct.cell_types.erase("$sshl");
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cone_ct.cell_types.erase("$sshr");
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modwalker.setup(design, module);
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find_shareable_cells();
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if (shareable_cells.size() < 2)
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return;
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log("Found %d cells in module %s that may be considered for resource sharing.\n",
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int(shareable_cells.size()), log_id(module));
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while (!shareable_cells.empty())
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{
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RTLIL::Cell *cell = *shareable_cells.begin();
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shareable_cells.erase(cell);
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log(" Analyzing resource sharing options for %s:\n", log_id(cell));
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std::vector<RTLIL::Cell*> candidates;
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find_shareable_partners(candidates, cell);
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if (candidates.empty()) {
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log(" No candidates found.\n");
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continue;
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}
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log(" Found %d candidates:", int(candidates.size()));
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for (auto c : candidates)
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log(" %s", log_id(c));
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log("\n");
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &cell_activation_patterns = find_cell_activation_patterns(cell);
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RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
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log(" Found %d activation_patterns using ctrl signal %s.\n", int(cell_activation_patterns.size()), log_signal(cell_activation_signals));
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if (cell_activation_patterns.empty())
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continue;
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for (auto other_cell : candidates)
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{
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log(" Analyzing resource sharing with %s:\n", log_id(other_cell));
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell);
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RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
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log(" Found %d activation_patterns using ctrl signal %s.\n",
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int(other_cell_activation_patterns.size()), log_signal(other_cell_activation_signals));
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if (other_cell_activation_patterns.empty())
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continue;
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ezDefaultSAT ez;
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SatGen satgen(&ez, &modwalker.sigmap);
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std::set<RTLIL::Cell*> sat_cells;
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std::set<RTLIL::SigBit> bits_queue;
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std::vector<int> cell_active, other_cell_active;
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RTLIL::SigSpec all_ctrl_signals;
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for (auto &p : cell_activation_patterns) {
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log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
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cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
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all_ctrl_signals.append(p.first);
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}
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for (auto &p : other_cell_activation_patterns) {
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log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
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other_cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
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all_ctrl_signals.append(p.first);
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}
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for (auto &bit : cell_activation_signals.to_sigbit_vector())
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bits_queue.insert(bit);
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for (auto &bit : other_cell_activation_signals.to_sigbit_vector())
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bits_queue.insert(bit);
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while (!bits_queue.empty())
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{
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std::set<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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bits_queue.clear();
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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// log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type));
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satgen.importCell(pbit.cell);
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sat_cells.insert(pbit.cell);
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}
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}
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all_ctrl_signals.sort_and_unify();
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std::vector<int> sat_model = satgen.importSigSpec(all_ctrl_signals);
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std::vector<bool> sat_model_values;
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ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active)));
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log(" Size of SAT problem: %d cells, %d variables, %d clauses\n",
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int(sat_cells.size()), ez.numCnfVariables(), ez.numCnfClauses());
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if (ez.solve(sat_model, sat_model_values)) {
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log(" According to the SAT solver this pair of cells can not be shared.\n");
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log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), int(sat_model_values.size()));
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for (int i = int(sat_model_values.size())-1; i >= 0; i--)
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log("%c", sat_model_values[i] ? '1' : '0');
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log("\n");
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continue;
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}
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log(" According to the SAT solver this pair of cells can be shared.\n");
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log(" WARNING: Actually sharing the cells is not implemented yet.\n");
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shareable_cells.erase(other_cell);
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break;
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}
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}
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}
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};
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struct SharePass : public Pass {
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SharePass() : Pass("share", "perform sat-based resource sharing") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" share [options] [selection]\n");
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log("\n");
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log("This pass merges shareable resources into a single resource. A SAT solver\n");
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log("is used to determine if two resources are share-able.\n");
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log("\n");
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log(" -all\n");
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log(" Per default the selection of cells that is considered for sharing is\n");
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log(" narrowed using some built-in heuristics. With this option all selected\n");
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log(" cells are considered for resource sharing.\n");
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log("\n");
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log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n");
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log(" state must be selected!\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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ShareWorkerConfig config;
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||||
config.opt_all = false;
|
||||
|
||||
log_header("Executing SHARE pass (SAT-based resource sharing).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-all") {
|
||||
config.opt_all = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto &mod_it : design->modules)
|
||||
if (design->selected(mod_it.second))
|
||||
ShareWorker(config, design, mod_it.second);
|
||||
}
|
||||
} SharePass;
|
||||
|
||||
Loading…
Reference in New Issue