mirror of https://github.com/YosysHQ/yosys.git
Improved inout handling in equiv_make
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@ -280,7 +280,7 @@ struct EquivMakeWorker
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for (auto c : cells_list)
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for (auto &conn : c->connections())
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if (ct.cell_input(c->type, conn.first)) {
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if (!ct.cell_output(c->type, conn.first)) {
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SigSpec old_sig = assign_map(conn.second);
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SigSpec new_sig = rd_signal_map(old_sig);
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if (old_sig != new_sig) {
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