mirror of https://github.com/YosysHQ/yosys.git
Renamed "aig" to "aigmap"
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85287295b2
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@ -18,7 +18,7 @@ OBJS += passes/techmap/dff2dffe.o
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OBJS += passes/techmap/dffinit.o
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OBJS += passes/techmap/pmuxtree.o
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OBJS += passes/techmap/muxcover.o
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OBJS += passes/techmap/aig.o
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OBJS += passes/techmap/aigmap.o
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endif
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GENFILES += passes/techmap/techmap.inc
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@ -23,12 +23,12 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AigPass : public Pass {
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AigPass() : Pass("aig", "convert logic to and-inverter circuit") { }
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struct AigmapPass : public Pass {
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AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { }
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virtual void help()
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{
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log("\n");
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log(" aig [options] [selection]\n");
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log(" aigmap [options] [selection]\n");
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log("\n");
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log("Replace all logic cells with circuits made of only $_AND_ and\n");
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log("$_NOT_ cells.\n");
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@ -41,7 +41,7 @@ struct AigPass : public Pass {
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{
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bool nand_mode = false;
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log_header("Executing AIG pass (converting logic to AIG).\n");
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log_header("Executing AIGMAP pass (map logic to AIG).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -144,6 +144,6 @@ struct AigPass : public Pass {
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module->remove(cell);
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}
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}
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} AigPass;
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} AigmapPass;
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PRIVATE_NAMESPACE_END
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@ -536,8 +536,8 @@ struct TestCellPass : public Pass {
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log(" -simlib\n");
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log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
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log("\n");
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log(" -aig\n");
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log(" instead of calling \"techmap\", call \"aig\"\n");
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log(" -aigmap\n");
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log(" instead of calling \"techmap\", call \"aigmap\"\n");
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log("\n");
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log(" -muxdiv\n");
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log(" when creating test benches with dividers, create an additional mux\n");
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@ -603,8 +603,8 @@ struct TestCellPass : public Pass {
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techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
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continue;
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}
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if (args[argidx] == "-aig") {
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techmap_cmd = "aig";
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if (args[argidx] == "-aigmap") {
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techmap_cmd = "aigmap";
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continue;
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}
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if (args[argidx] == "-muxdiv") {
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