mirror of https://github.com/YosysHQ/yosys.git
Add xilinx_dsp for register packing
This commit is contained in:
Eddie Hung
parent
42f8e68e76
commit
dd59375a66
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/ice40_dsp_pm.h
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/peepopt_pm.h
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/%_pm.h
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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void create_xilinx_dsp(xilinx_dsp_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp;
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#if 0
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log("\n");
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("mul: %s\n", log_id(st.mul, "--"));
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log("ffY: %s\n", log_id(st.ffY, "--"));
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#endif
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log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.mul));
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Cell *cell = st.mul;
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log_assert(cell);
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// Input Interface
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cell->setPort("\\A", st.sigA);
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cell->setPort("\\B", st.sigB);
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cell->setParam("\\AREG", st.ffA ? State::S1 : State::S0);
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cell->setParam("\\BREG", st.ffB ? State::S1 : State::S0);
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if (st.clock != SigBit())
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{
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cell->setPort("\\CLK", st.clock);
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if (st.ffA) {
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cell->setParam("\\AREG", State::S1);
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cell->setPort("\\CEA2", State::S1);
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}
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if (st.ffB) {
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cell->setParam("\\BREG", State::S1);
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cell->setPort("\\CEA2", State::S1);
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}
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if (st.ffY) {
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cell->setPort("\\PREG", State::S1);
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cell->setPort("\\CEP", State::S1);
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}
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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if (st.ffA)
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log(" ffA:%s", log_id(st.ffA));
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if (st.ffB)
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log(" ffB:%s", log_id(st.ffB));
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if (st.ffY)
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log(" ffY:%s", log_id(st.ffY));
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log("\n");
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}
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// Output Interface
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pm.autoremove(st.ffY);
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}
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struct Ice40DspPass : public Pass {
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Ice40DspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" xilinx_dsp [options] [selection]\n");
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log("\n");
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log("Pack registers into Xilinx DSPs\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(create_xilinx_dsp);
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}
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} Ice40DspPass;
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PRIVATE_NAMESPACE_END
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pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> sigA sigB sigY sigS
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state <Cell*> addAB muxAB
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match mul
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select mul->type.in($__MUL25X18)
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endmatch
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match ffA
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select ffA->type.in($dff) /* TODO: $dffe */
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// select nusers(port(ffA, \Q)) == 2
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index <SigSpec> port(ffA, \Q) === port(mul, \A)
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// DSP48E1 does not support clock inversion
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index <SigBit> port(ffA, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigA clock
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sigA = port(mul, \A);
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if (ffA) {
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sigA = port(ffA, \D);
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clock = port(ffA, \CLK).as_bit();
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}
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endcode
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match ffB
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select ffB->type.in($dff)
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// select nusers(port(ffB, \Q)) == 2
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index <SigSpec> port(ffB, \Q) === port(mul, \B)
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index <SigBit> port(ffB, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigB clock
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sigB = port(mul, \B);
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if (ffB) {
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sigB = port(ffB, \D);
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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match ffY
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select ffY->type.in($dff)
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select nusers(port(ffY, \D)) == 2
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index <SigSpec> port(ffY, \D) === port(mul, \Y)
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index <SigBit> port(ffY, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigY clock
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sigY = port(mul, \Y);
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if (ffY) {
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sigY = port(ffY, \Q);
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SigBit c = port(ffY, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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