mirror of https://github.com/YosysHQ/yosys.git
Fixed detection of major wires in opt_clean
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@ -112,6 +112,9 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
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if (w1->port_input != w2->port_input)
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return w2->port_input;
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if (w1->port_output != w2->port_output)
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return w2->port_output;
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if (w1->name[0] != w2->name[0])
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return w2->name[0] == '\\';
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