mirror of https://github.com/YosysHQ/yosys.git
Added abc -keepff option
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de3ea9269a
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3121d19d95
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@ -109,7 +109,7 @@ static void mark_port(RTLIL::SigSpec sig)
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}
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}
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static void extract_cell(RTLIL::Cell *cell)
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static void extract_cell(RTLIL::Cell *cell, bool keepff)
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{
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if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
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{
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@ -121,6 +121,11 @@ static void extract_cell(RTLIL::Cell *cell)
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RTLIL::SigSpec sig_d = cell->connections["\\D"];
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RTLIL::SigSpec sig_q = cell->connections["\\Q"];
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if (keepff)
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for (auto &c : sig_q.chunks)
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if (c.wire != NULL)
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c.wire->attributes["\\keep"] = 1;
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assign_map.apply(sig_d);
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assign_map.apply(sig_q);
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@ -403,7 +408,7 @@ static std::string fold_abc_cmd(std::string str)
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}
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static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str)
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std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff)
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{
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module = current_module;
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map_autoidx = RTLIL::autoidx++;
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@ -498,7 +503,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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if (design->selected(current_module, it.second))
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cells.push_back(it.second);
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for (auto c : cells)
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extract_cell(c);
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extract_cell(c, keepff);
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for (auto &wire_it : module->wires) {
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if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
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@ -940,6 +945,10 @@ struct AbcPass : public Pass {
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log(" with -dff, then it falls back to the automatic dection of clock domain\n");
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log(" if the specified clock is not found in a module.)\n");
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log("\n");
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log(" -keepff\n");
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log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
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log(" them, for example for equivialence checking.)\n");
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log("\n");
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log(" -nocleanup\n");
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log(" when this option is used, the temporary files created by this pass\n");
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log(" are not removed. this is useful for debugging.\n");
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@ -960,7 +969,7 @@ struct AbcPass : public Pass {
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std::string exe_file = rewrite_yosys_exe("yosys-abc");
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std::string script_file, liberty_file, constr_file, clk_str;
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bool dff_mode = false, cleanup = true;
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bool dff_mode = false, keepff = false, cleanup = true;
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int lut_mode = 0;
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size_t argidx;
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@ -1001,6 +1010,10 @@ struct AbcPass : public Pass {
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clk_str = args[++argidx];
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continue;
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}
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if (arg == "-keepff") {
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keepff = true;
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continue;
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}
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if (arg == "-nocleanup") {
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cleanup = false;
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continue;
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@ -1020,7 +1033,7 @@ struct AbcPass : public Pass {
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if (mod_it.second->processes.size() > 0)
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log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
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else
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abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str);
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abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff);
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}
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assign_map.clear();
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