mirror of https://github.com/YosysHQ/yosys.git
Bugfix in iopadmap
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@ -164,8 +164,10 @@ struct IopadmapPass : public Pass {
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log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
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RTLIL::Wire *new_wire = NULL;
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if (!portname2.empty())
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if (!portname2.empty()) {
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new_wire = module->addWire(NEW_ID, wire);
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module->swap_names(new_wire, wire);
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}
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if (flag_bits)
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{
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