mirror of https://github.com/YosysHQ/yosys.git
Some cleanups in opt_rmdff
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parent
badc5f7eb9
commit
2a613b1b66
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@ -130,38 +130,31 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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if (sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (val_rv.bits.size() == 0)
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val_rv = val_init;
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connect(conn);
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connect(conn);
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
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RTLIL::SigSig conn(sig_q, val_init);
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mod->connect(conn);
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mod->connect(sig_q, val_init);
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goto delete_dff;
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}
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if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
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RTLIL::SigSig conn(sig_q, sig_d);
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mod->connect(conn);
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log_dump(sig_q, sig_d);
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mod->connect(sig_q, sig_d);
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goto delete_dff;
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}
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if (sig_d == sig_q && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (sig_r.size()) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connect(conn);
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}
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if (has_init) {
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RTLIL::SigSig conn(sig_q, val_init);
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mod->connect(conn);
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}
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if (sig_r.size())
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mod->connect(sig_q, val_rv);
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if (has_init)
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mod->connect(sig_q, val_init);
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goto delete_dff;
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}
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