mirror of https://github.com/YosysHQ/yosys.git
expose command to not skip 'internal' wires beginning with '$'
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@ -42,7 +42,7 @@ struct dff_map_bit_info_t {
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bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
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{
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if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
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if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name))
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return false;
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if (wire->port_input)
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return false;
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