mirror of https://github.com/YosysHQ/yosys.git
Fixes in fsm detect/extract for better detection of non-fsm circuits
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@ -161,7 +161,7 @@ struct FsmDetectPass : public Pass {
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sig_at_port.clear();
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for (auto &cell_it : module->cells)
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for (auto &conn_it : cell_it.second->connections) {
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if (ct.cell_output(cell_it.second->type, conn_it.first)) {
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if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
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@ -144,8 +144,8 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d
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return;
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}
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assert(undef.width > 0);
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assert(ce.stop_signals.check_all(undef));
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log_assert(undef.width > 0);
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log_assert(ce.stop_signals.check_all(undef));
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undef = undef.extract(0, 1);
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constval = undef;
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@ -361,7 +361,7 @@ struct FsmExtractPass : public Pass {
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sig2trigger.clear();
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for (auto &cell_it : module->cells)
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for (auto &conn_it : cell_it.second->connections) {
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if (ct.cell_output(cell_it.second->type, conn_it.first)) {
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if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
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