mirror of https://github.com/YosysHQ/yosys.git
Added equiv_make command
This commit is contained in:
Clifford Wolf
parent
e13a45ae61
commit
76c5d863c5
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@ -1618,6 +1618,15 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a
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return cell;
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}
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RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
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{
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RTLIL::Cell *cell = addCell(name, "$equiv");
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cell->setPort("\\A", sig_a);
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cell->setPort("\\B", sig_b);
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cell->setPort("\\Y", sig_y);
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return cell;
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}
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RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
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{
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RTLIL::Cell *cell = addCell(name, "$sr");
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@ -439,7 +439,7 @@ namespace RTLIL
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return result;
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}
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pool<T> to_set() const { return *this; }
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pool<T> to_pool() const { return *this; }
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std::vector<T> to_vector() const { return *this; }
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};
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};
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@ -968,6 +968,7 @@ public:
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RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
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RTLIL::Cell* addLut (RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut);
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RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
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RTLIL::Cell* addEquiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
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RTLIL::Cell* addSr (RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true);
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RTLIL::Cell* addDff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true);
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@ -4,4 +4,5 @@ OBJS += passes/sat/freduce.o
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OBJS += passes/sat/eval.o
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OBJS += passes/sat/miter.o
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OBJS += passes/sat/expose.o
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OBJS += passes/sat/equiv_make.o
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@ -0,0 +1,248 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivMakeWorker
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{
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Module *gold_mod, *gate_mod, *equiv_mod;
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pool<IdString> wire_names, cell_names;
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CellTypes ct;
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void copy_to_equiv()
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{
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Module *gold_clone = gold_mod->clone();
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Module *gate_clone = gate_mod->clone();
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for (auto it : gold_clone->wires().to_vector()) { if (it->name[0] == '\\') wire_names.insert(it->name); gold_clone->rename(it, it->name.str() + "_gold"); }
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for (auto it : gold_clone->cells().to_vector()) { if (it->name[0] == '\\') cell_names.insert(it->name); gold_clone->rename(it, it->name.str() + "_gold"); }
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for (auto it : gate_clone->wires().to_vector()) { if (it->name[0] == '\\') wire_names.insert(it->name); gate_clone->rename(it, it->name.str() + "_gate"); }
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for (auto it : gate_clone->cells().to_vector()) { if (it->name[0] == '\\') cell_names.insert(it->name); gate_clone->rename(it, it->name.str() + "_gate"); }
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gold_clone->cloneInto(equiv_mod);
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gate_clone->cloneInto(equiv_mod);
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delete gold_clone;
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delete gate_clone;
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}
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void find_same_wires()
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{
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SigMap assign_map(equiv_mod);
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SigMap rd_signal_map;
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// list of cells without added $equiv cells
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auto cells_list = equiv_mod->cells().to_vector();
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for (auto id : wire_names)
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{
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IdString gold_id = id.str() + "_gold";
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IdString gate_id = id.str() + "_gate";
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Wire *gold_wire = equiv_mod->wire(gold_id);
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Wire *gate_wire = equiv_mod->wire(gate_id);
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if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) {
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if (gold_wire && gold_wire->port_id)
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log_error("Can't match gold port `%s' to a gate port.\n", log_id(gold_wire));
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if (gate_wire && gate_wire->port_id)
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log_error("Can't match gate port `%s' to a gold port.\n", log_id(gate_wire));
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continue;
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}
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log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n",
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log_id(gold_wire), log_signal(assign_map(gold_wire)),
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log_id(gate_wire), log_signal(assign_map(gate_wire)), log_id(id));
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if (gold_wire->port_output || gate_wire->port_output)
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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wire->port_output = true;
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gold_wire->port_input = false;
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gate_wire->port_input = false;
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gold_wire->port_output = false;
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gate_wire->port_output = false;
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for (int i = 0; i < wire->width; i++)
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equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
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rd_signal_map.add(assign_map(gold_wire), wire);
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rd_signal_map.add(assign_map(gate_wire), wire);
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}
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else
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if (gold_wire->port_input || gate_wire->port_input)
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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wire->port_input = true;
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gold_wire->port_input = false;
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gate_wire->port_input = false;
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equiv_mod->connect(gold_wire, wire);
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equiv_mod->connect(gate_wire, wire);
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}
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else
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{
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Wire *wire = equiv_mod->addWire(id, gold_wire->width);
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for (int i = 0; i < wire->width; i++)
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equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
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rd_signal_map.add(assign_map(gold_wire), wire);
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rd_signal_map.add(assign_map(gate_wire), wire);
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}
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}
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for (auto c : cells_list)
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for (auto &conn : c->connections())
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if (ct.cell_input(c->type, conn.first)) {
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SigSpec old_sig = assign_map(conn.second);
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SigSpec new_sig = rd_signal_map(old_sig);
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if (old_sig != new_sig) {
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log("Changing input %s of cell %s (%s): %s -> %s\n",
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log_id(conn.first), log_id(c), log_id(c->type),
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log_signal(old_sig), log_signal(new_sig));
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c->setPort(conn.first, new_sig);
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}
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}
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equiv_mod->fixup_ports();
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}
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void find_same_cells()
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{
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SigMap assign_map(equiv_mod);
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for (auto id : cell_names)
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{
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IdString gold_id = id.str() + "_gold";
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IdString gate_id = id.str() + "_gate";
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Cell *gold_cell = equiv_mod->cell(gold_id);
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Cell *gate_cell = equiv_mod->cell(gate_id);
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if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) ||
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gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections()))
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try_next_cell_name:
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continue;
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for (auto gold_conn : gold_cell->connections())
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if (!gate_cell->connections().count(gold_conn.first))
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goto try_next_cell_name;
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log("Presumably equivalent cells: %s %s (%s) -> %s\n",
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log_id(gold_cell), log_id(gate_cell), log_id(gold_cell->type), log_id(id));
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for (auto gold_conn : gold_cell->connections())
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{
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SigSpec gold_sig = assign_map(gold_conn.second);
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SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first));
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if (ct.cell_output(gold_cell->type, gold_conn.first)) {
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equiv_mod->connect(gate_sig, gold_sig);
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continue;
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}
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for (int i = 0; i < GetSize(gold_sig); i++)
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if (gold_sig[i] != gate_sig[i]) {
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Wire *w = equiv_mod->addWire(NEW_ID);
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equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
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gold_sig[i] = w;
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}
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gold_cell->setPort(gold_conn.first, gold_sig);
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}
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equiv_mod->remove(gate_cell);
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equiv_mod->rename(gold_cell, id);
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}
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}
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void run()
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{
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copy_to_equiv();
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find_same_wires();
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find_same_cells();
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}
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};
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struct EquivMakePass : public Pass {
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EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_make [options] gold_module gate_module equiv_module\n");
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log("\n");
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log("This creates a module annotated with $equiv cells from two presumably\n");
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log("equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'\n");
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log("to work with the created equivalent checking module.\n");
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log("\n");
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log("Note: The circuit created by this command is not a miter (with something like\n");
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log("a trigger output), but instead uses $equiv cells to encode the equivalence\n");
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log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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EquivMakeWorker worker;
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worker.ct.setup(design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-foo" && argidx+1 < args.size()) {
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// log("foo> %s\n", args[++argidx].c_str());
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// continue;
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// }
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break;
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}
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if (argidx+3 != args.size())
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log_cmd_error("Invalid number of arguments.\n");
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worker.gold_mod = design->module(RTLIL::escape_id(args[argidx]));
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worker.gate_mod = design->module(RTLIL::escape_id(args[argidx+1]));
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worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2]));
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if (worker.gold_mod == nullptr)
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log_cmd_error("Can't find gold module %s.\n", args[argidx].c_str());
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if (worker.gate_mod == nullptr)
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log_cmd_error("Can't find gate module %s.\n", args[argidx+1].c_str());
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if (worker.equiv_mod != nullptr)
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log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str());
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if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes())
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log_cmd_error("Gold module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
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if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes())
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log_cmd_error("Gate module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
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log_header("Executing EQUIV_MAKE pass (creating equiv checking module).\n");
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worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
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worker.run();
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}
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} EquivMakePass;
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PRIVATE_NAMESPACE_END
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