mirror of https://github.com/YosysHQ/yosys.git
Revert "abc9 to write_xaiger -symbols, not -map"
This reverts commit 04429f8152
.
This commit is contained in:
parent
7ad9628f07
commit
2811d66dea
|
@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
|
||||
handle_loops(design);
|
||||
|
||||
Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str()));
|
||||
Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
|
||||
|
||||
// Now 'unexpose' those wires by undoing
|
||||
// the expose operation -- remove them from PO/PI
|
||||
|
@ -518,7 +518,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
bool builtin_lib = liberty_file.empty();
|
||||
RTLIL::Design *mapped_design = new RTLIL::Design;
|
||||
//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
|
||||
AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */);
|
||||
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
|
||||
AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
|
||||
reader.parse_xaiger();
|
||||
|
||||
ifs.close();
|
||||
|
|
Loading…
Reference in New Issue