mirror of https://github.com/YosysHQ/yosys.git
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
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@ -158,7 +158,7 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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PRIVATE_NAMESPACE_END
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell)
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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{
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if (cell->type.in("$not", "$pos")) {
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bitwise_unary_op(this, cell);
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@ -29,7 +29,7 @@ struct AbstractCellEdgesDatabase
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{
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virtual ~AbstractCellEdgesDatabase() { }
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virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
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bool add_cell(RTLIL::Cell *cell);
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bool add_edges_from_cell(RTLIL::Cell *cell);
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};
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struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
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@ -344,7 +344,7 @@ static void run_edges_test(RTLIL::Design *design, bool verbose)
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SatGen satgen(&ez, &sigmap);
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FwdCellEdgesDatabase edges_db(sigmap);
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if (!edges_db.add_cell(cell))
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if (!edges_db.add_edges_from_cell(cell))
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log_error("Creating edge database failed for this cell!\n");
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dict<SigBit, pool<SigBit>> satgen_db;
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