Fixed a verilog parser memory leak

2016-07-25 16:37:58 +02:00 · 2016-07-25 16:37:58 +02:00 · 5b944ef11b
parent 7a67add95d
commit 5b944ef11b
1 changed files with 1 additions and 0 deletions
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@ -880,6 +880,7 @@ cell_port_list:
 			if (!node->children.empty()) break;
 			if (!node->str.empty()) break;
 			astbuf2->children.pop_back();
+			delete node;
 		}

 		// check port types