diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d1da630d5..4cb65a088 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -880,6 +880,7 @@ cell_port_list:
 			if (!node->children.empty()) break;
 			if (!node->str.empty()) break;
 			astbuf2->children.pop_back();
+			delete node;
 		}
 
 		// check port types