whitequark
fd21564deb
flowmap: improve debug graph output. NFC.
2019-01-04 03:30:04 +00:00
whitequark
7850a0c28a
flowmap: add link to longer version of paper. NFC.
2019-01-04 02:33:10 +00:00
Clifford Wolf
d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap
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flowmap: new techmap pass
2019-01-03 17:03:18 +01:00
whitequark
07af772a72
flowmap: new techmap pass.
2019-01-03 14:28:19 +00:00
Clifford Wolf
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp
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opt_expr: refactor and improve simplification of comparisons
2019-01-02 17:34:04 +01:00
whitequark
bf8db55ef3
opt_expr: improve simplification of comparisons with large constants.
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The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.
However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.
This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
2019-01-02 15:45:28 +00:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
Clifford Wolf
2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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opt_lut: elimination fixes
2019-01-02 15:45:29 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
c55dfb8369
opt_lut: reflect changes in sigmap.
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Otherwise, some LUTs will be missed during elimination.
2019-01-02 10:21:58 +00:00
whitequark
06143ab33f
opt_lut: use a worklist, and revisit cells affected by elimination.
2019-01-02 09:36:32 +00:00
whitequark
f7363ac508
opt_lut: count eliminated cells, and set opt.did_something for them.
2019-01-02 09:14:43 +00:00
whitequark
4fd458290c
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
2019-01-02 05:11:29 +00:00
whitequark
9e9846a6ea
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
2019-01-02 03:01:25 +00:00
whitequark
8e53d2e0bf
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
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Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
2019-01-02 02:45:49 +00:00
whitequark
42c356c49c
opt_lut: eliminate LUTs evaluating to constants or inputs.
2018-12-31 23:55:40 +00:00
Clifford Wolf
0a840dd883
Fix handling of (* keep *) wires in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-31 16:37:40 +01:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
b784440857
proc_clean: remove any empty cases at the end of the switch.
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Previously, only completely empty switches were removed.
2018-12-22 09:04:46 +00:00
whitequark
0c318e7db5
memory_collect: do not truncate 'x from \INIT.
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The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
2018-12-21 02:01:27 +00:00
David Shah
2b16d4ed3d
memory_dff: Fix typo when checking init value
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-18 17:40:01 +00:00
Icenowy Zheng
256fb8c95c
Add "dffinit -noreinit" parameter
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Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.
Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:10:40 +08:00
Icenowy Zheng
fec8b3c81f
Add "dffinit -strinit high low"
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On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".
Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 15:37:43 +08:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:31 +01:00
Clifford Wolf
ddff75b60a
Merge pull request #736 from whitequark/select_assert_list
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select: print selection if a -assert-* flag causes an error
2018-12-16 16:45:49 +01:00
whitequark
f6412d7109
select: print selection if a -assert-* flag causes an error.
2018-12-16 15:44:29 +00:00
Clifford Wolf
0d9c850a07
Merge pull request #735 from daveshah1/trifixes
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deminout fixes
2018-12-16 16:02:21 +01:00
Clifford Wolf
f53e19cc71
Fix equiv_opt indenting
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 15:57:28 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
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memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
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Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
Clifford Wolf
19ca4e2ac3
Merge pull request #722 from whitequark/rename_src
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rename: add -src, for inferring names from source locations
2018-12-16 15:28:29 +01:00
Clifford Wolf
556341a77f
Merge pull request #720 from whitequark/master
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lut2mux: handle 1-bit INIT constant in $lut cells
2018-12-16 15:27:23 +01:00
David Shah
4c59447168
deminout: Consider $tribuf cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
Graham Edgecombe
4fef9689ab
memory_bram: Fix initdata bit order after shuffling
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In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.
This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).
This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
2018-12-11 21:02:49 +00:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
whitequark
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
whitequark
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
whitequark
9eb03d458d
opt_lut: show original truth table for both cells.
2018-12-07 17:04:41 +00:00
whitequark
a8ab722824
opt_lut: add -limit option, for debugging misoptimizations.
2018-12-07 16:36:26 +00:00
David Shah
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
Clifford Wolf
643f858acf
Bugfix in opt_expr handling of a<0 and a>=0
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:21 +01:00
whitequark
a9baee4b24
rename: add -src, for inferring names from source locations.
2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
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This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
whitequark
88217d0157
opt_lut: simplify type conversion. NFC.
2018-12-05 19:12:02 +00:00
Clifford Wolf
2d98db73e3
Rename opt_lut.cpp to opt_lut.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-05 18:03:58 +01:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
e603484070
opt_lut: always prefer to eliminate 1-LUTs.
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These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
2018-12-05 16:30:37 +00:00
whitequark
59eea0183f
opt_lut: collect and display statistics.
2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c
opt_lut: refactor to use a worker. NFC.
2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 16:30:37 +00:00
Clifford Wolf
c800e3bb16
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-04 23:30:23 +01:00
Clifford Wolf
70c417174d
Merge pull request #702 from smunaut/min_ce_use
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Add option to only use DFFE is the resulting E signal would be use > N times
2018-12-04 14:29:21 -08:00
Clifford Wolf
47c89d600c
Merge pull request #676 from rafaeltp/master
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Splits SigSpec into bits before calling check_signal_in_fanout (solves #675 )
2018-12-01 04:11:19 +01:00
Sylvain Munaut
8d3ab626ea
dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
ab97eddee9
Add iteration limit to "opt_muxtree"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-20 17:56:47 +01:00
Niels Moseley
cfc9b9147c
DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.
2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696
Liberty file newline handling is more relaxed. More descriptive error message
2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a
Report an error when a liberty file contains pin references that reference non-existing pins
2018-11-03 18:07:51 +01:00
rafaeltp
f8b97e21f3
using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal
2018-10-21 11:32:44 -07:00
rafaeltp
7b964bfb83
cleaning up for PR
2018-10-20 18:02:59 -07:00
rafaeltp
ce069830c5
fixing code style
2018-10-20 17:57:26 -07:00
rafaeltp
0ad4321781
solves #675
2018-10-20 17:50:21 -07:00
Ruben Undheim
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
Clifford Wolf
6514443a5c
Merge pull request #672 from daveshah1/fix_bram
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memory_bram: Reset make_outreg when growing read ports
2018-10-19 16:09:11 +02:00
David Shah
3420ae5ca5
memory_bram: Reset make_outreg when growing read ports
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 14:46:31 +01:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
tklam
f4343b3dc7
stop check_signal_in_fanout from traversing FFs
2018-10-13 23:24:24 +08:00
tklam
302edf0429
stop check_signal_in_fanout from traversing FFs
2018-10-13 23:11:19 +08:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
tklam
b86eb3deef
fix bug: pass by reference
2018-09-26 17:57:39 +08:00
TK Lam
2b89074240
Fix issue #639
2018-09-26 16:11:45 +08:00
Clifford Wolf
592a82c0ad
Merge pull request #625 from aman-goel/master
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Minor revision to -expose in setundef pass
2018-09-14 12:36:13 +02:00
acw1251
5fe16c25b8
Fixed minor typo in "sim" help message
2018-09-12 18:34:27 -04:00
Aman Goel
75c1f8d241
Minor revision to -expose in setundef pass
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Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
2018-09-10 21:44:36 -04:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d87c7df27f
Two passes are not allowed to have the same filename
2018-08-20 15:28:09 +02:00
Benedikt Tutzer
6d18837d62
Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path
2018-08-20 15:11:06 +02:00
Clifford Wolf
05466790a6
Merge pull request #606 from cr1901/show-win
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`show` pass `-format` and `-viewer` improvements on Windows
2018-08-19 15:25:46 +02:00
Aman Goel
83b41260f6
Revision to expose option in setundef pass
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Corrects indentation
Simplifications and corrections
2018-08-18 09:08:07 +05:30
Aman Goel
61f002c908
Merge pull request #3 from YosysHQ/master
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Updates from official repo
2018-08-18 08:18:40 +05:30
Benedikt Tutzer
d79a2808cf
Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script
2018-08-16 16:00:11 +02:00
William D. Jones
7ce7ea2eb4
Update show pass documentation with Windows caveats.
2018-08-15 17:18:19 -04:00
William D. Jones
9f91c62348
Fix run_command() when using -format and -viewer in show pass.
2018-08-15 17:18:19 -04:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
87aef8f0cc
Add async2sync pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-19 15:31:12 +02:00
Aman Goel
5dcb899e76
Merge pull request #2 from YosysHQ/master
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Merging with official repo
2018-07-18 11:34:18 -04:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
Aman Goel
4d343fc1cd
Merging with official repo
2018-07-04 15:14:28 -04:00
Clifford Wolf
5f2bc1ce76
Add automatic verific import in hierarchy command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Edmond Cote
d89560a0ba
Include module name for area summary stats
...
The PR prints the name of the module when displaying the final area count.
Pros:
- Easier for the user to `grep` for area information about a specific module
Cons:
- Arguably more verbose, less "pretty" than author desires
Verification:
~~~~
30c30
< Chip area for this module: 20616.349000
---
> Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
< Chip area for this module: 88.697700
---
> Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
< Chip area for this module: 20705.046700
---
> Chip area for top module '\picorv32_axi': 20705.046700
~~~~
2018-06-18 17:29:01 -07:00
Clifford Wolf
f273291dfe
Add setundef -anyseq / -anyconst support to -undriven mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:57:28 +02:00
Clifford Wolf
4cd6d5556a
Add "setundef -anyconst"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 11:49:58 +02:00
Clifford Wolf
3ab79a231b
Bugfix in handling of array instances with empty ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-31 18:09:31 +02:00
Clifford Wolf
cee4b1e6bc
Disable memory_dff for initialized FFs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 17:16:15 +02:00
Clifford Wolf
74efafc1cf
Add some cleanup code to memory_nordff
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 16:42:06 +02:00
Robert Ou
9763e4d830
Fix infinite loop in abc command under emscripten
2018-05-18 22:42:39 -07:00
Robert Ou
bfce3a7479
Add an option to statically link abc into yosys
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This is currently incomplete because the output filter no longer works.
2018-05-18 22:35:28 -07:00
Aman Goel
6e63df6dd0
Correction to -expose with setundef
2018-05-15 13:06:23 -04:00
Clifford Wolf
fe80b39f56
Fix iopadmap for loops between tristate IO buffers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 14:02:27 +02:00
Clifford Wolf
edd297fb1c
Fix iopadmap for cases where IO pins already have buffers on them
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 13:13:43 +02:00
Aman Goel
8b9a8c7f91
Minor correction
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Minor typo error correction in -expose with setundef
2018-05-14 18:58:49 -04:00
Aman Goel
b4a303a1b7
Corrections to option -expose in setundef pass
2018-05-13 20:13:54 -04:00
Aman Goel
9286acb687
Add option -expose to setundef pass
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Option -expose converts undriven wires to inputs.
Example usage: setundef -undriven -expose [selection]
2018-05-13 16:53:35 -04:00
Clifford Wolf
0fad1570b5
Some cleanups in setundef.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-13 16:36:12 +02:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
.
2018-05-13 13:06:36 +02:00
Clifford Wolf
587056447e
Add optimization of tristate buffer with constant control input
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-12 15:18:27 +02:00
Clifford Wolf
11406a8082
Add "hierarchy -simcheck"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-12 13:59:13 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
145c685de0
Add ABC FAQ to "help abc"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 21:59:31 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Clifford Wolf
705c366a91
Added missing dont_use handling for SR FFs to dfflibmap
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-05 11:01:45 +02:00
Clifford Wolf
665eec3d53
Removed $timescale from "sat" command VCD writer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-29 12:38:41 +02:00
Clifford Wolf
ee3c12d6d9
Chenged "extensions_map" to "extensions_list" in hierarchy.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 14:12:57 +02:00
Sergi Granell
f93f8aaa11
passes/hierarchy: Reduce code duplication in expand_module
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This also makes it easier to add new file extensions support.
Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
2018-03-27 09:35:20 +02:00
Clifford Wolf
491c352da7
Add .sv support to "hierarchy -libdir"
2018-03-26 21:19:00 +02:00
Clifford Wolf
08225f49a4
Add "expose -input"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:52 +01:00
Clifford Wolf
83ffb23739
Add "setundef -undef"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-12 13:52:35 +01:00
Clifford Wolf
a74f805ba0
Fix handling of src attributes in flatten
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 13:55:30 +01:00
Clifford Wolf
73c01dca65
Add "memory_nordff" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 23:31:51 +01:00
Clifford Wolf
61a9e2eeb3
Fix connwrappers help message
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:54:34 +01:00
Clifford Wolf
d31584c649
Add $dlatchsr support to clk2fflogic
2018-02-26 12:20:28 +01:00
Clifford Wolf
fba499b866
Fix opt_rmdff handling of $dlatchsr
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 11:46:05 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
717abc93a8
Recognize stand-alone obj pattern even when it contains a slash
2018-02-13 14:55:24 +01:00
Clifford Wolf
9337e4999d
Improve log messages in equiv_make
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-19 16:20:40 +01:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
446ccf1f05
Bugfix in hierarchy blackbox module port width handling
2018-01-07 16:35:22 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
fefb652d56
Merge pull request #480 from Fatsie/liberty_value_expression
...
Value of properties can be expression.
2018-01-04 13:30:00 +01:00
Clifford Wolf
2d140a44eb
Temporarily derive blackbox modules in hierarchy to evaluate port widths
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-04 13:23:29 +01:00
Staf Verhaegen
92eb841f0a
Value of properties can be expression.
...
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:
input_voltage(CMOS) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
Current implementation just parses the expression but no interpretation is done.
2018-01-03 21:37:17 +00:00
Clifford Wolf
6132e6e72a
Fix a bug in clk2fflogic memory handling
2017-12-14 03:05:55 +01:00
Clifford Wolf
590e6961cb
Add clk2fflogic memory support
2017-12-14 02:07:31 +01:00
Clifford Wolf
88182e46d7
Check for memories in clk2fflogic
2017-12-13 19:14:34 +01:00
Clifford Wolf
ca2adc30c9
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
4f31cb6dad
Add "ltp" command
2017-10-31 12:40:25 +01:00
Clifford Wolf
c238f45ecf
Fix memory corruption bug in opt_rmdff
2017-10-26 18:02:15 +02:00
Clifford Wolf
1e502ef5a0
Fix typo in opt_clean log message
2017-10-26 18:01:48 +02:00
Clifford Wolf
716dbc9274
Revert 90be0d8
as it causes endless loops for some designs
2017-10-14 11:57:25 +02:00
Kaj Tuomi
90be0d800b
Fix input vector for reduce cells.
2017-10-12 13:05:10 +03:00
Clifford Wolf
7c57d8fbb4
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
Clifford Wolf
3f22f48eeb
Add blackbox command
2017-10-04 18:30:42 +02:00
Andrew Zonenberg
2b65b65d70
Added missing "break"
2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c
Implemented off-chain support for extract_reduce
2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c
extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
2017-09-15 13:59:05 -07:00
Clifford Wolf
ce78717e36
Merge pull request #412 from azonenberg/reduce-fixes
...
extract_reduce: Fix segfault on "undriven" inputs
2017-09-14 22:36:25 +02:00
Robert Ou
ab1bf8d661
extract_reduce: Fix segfault on "undriven" inputs
...
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
2017-09-14 12:54:44 -07:00
Clifford Wolf
498526cc0b
Merge pull request #411 from azonenberg/counter-extraction-fixes
...
Various improvements and bug fixes to extract_counter
2017-09-14 21:44:26 +02:00
Andrew Zonenberg
66e8986ae7
Minor changes to opt_demorgan requested during code review
2017-09-14 10:35:25 -07:00
Andrew Zonenberg
367d6b2194
Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output
2017-09-14 10:27:10 -07:00
Andrew Zonenberg
c8f2f082c6
Added support for inferring counters with reset to full scale instead of zero
2017-09-14 10:26:43 -07:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
0484ad666d
Added support for inferring counters with active-low reset
2017-09-14 10:26:21 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Andrew Zonenberg
c4a70a8cc3
Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
2017-09-14 10:25:51 -07:00
Andrew Zonenberg
6da5d36968
Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved
2017-09-12 18:47:46 -07:00
Clifford Wolf
f9d023c53f
Add src attribute to extra cells generated by proc_dlatch
2017-09-09 10:18:08 +02:00
Clifford Wolf
7d41c5e177
Further improve extract_fa (but still buggy)
2017-09-02 16:39:17 +02:00
Clifford Wolf
18609f3df8
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 12:35:09 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
8dc6083de7
updated to use get_src_attribute() and set_src_attribute().
2017-08-31 14:51:56 -06:00
Andrew Zonenberg
ed1e3ed39b
extract_counter: Added optimizations to remove unused high-order bits
2017-08-30 18:15:12 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00
Andrew Zonenberg
3fc1b9f3fd
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
2017-08-28 22:18:57 -07:00
Andrew Zonenberg
46b01f05bb
Refactored extract_counter to be generic vs GreenPAK specific
2017-08-28 22:18:47 -07:00
Andrew Zonenberg
b5c15636c5
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
2017-08-28 22:18:34 -07:00
Clifford Wolf
908f34aafc
Rename recover_reduce to extract_reduce, fix args handling
2017-08-28 19:52:06 +02:00
Clifford Wolf
3aad3ed3da
Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce
2017-08-28 19:46:17 +02:00
Clifford Wolf
ebbb0e9479
Further improve extract_fa pass
2017-08-28 19:43:26 +02:00
Robert Ou
849b885775
recover_reduce: Update documentation
...
The documentation now describes the commands performed in the deleted
recover_reduce script.
2017-08-27 02:19:19 -07:00
Robert Ou
74d0f17fd4
recover_reduce: Reindent using tabs
2017-08-27 02:12:41 -07:00
Robert Ou
8a5887464c
recover_reduce: Rename recover_reduce_core to recover_reduce
...
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.
Also rename to .cc (rather than .cpp) for consistency.
2017-08-27 02:01:32 -07:00
Robert Ou
99dad40ed0
recover_reduce: Add driver script for the $reduce_* recover feature
...
Conflicts:
passes/techmap/Makefile.inc
2017-08-27 01:57:20 -07:00
Robert Ou
8b7dc792ee
recover_reduce_core: Finish implementing the core function
2017-08-27 01:56:49 -07:00
Robert Ou
fa310c98f8
recover_reduce_core: Initial commit
...
Conflicts:
passes/techmap/Makefile.inc
2017-08-27 01:56:49 -07:00
Clifford Wolf
68c42f3a19
Don't track , ... contradictions through x/z-bits
2017-08-25 16:18:17 +02:00
Clifford Wolf
db6d78a186
Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr
2017-08-25 16:02:15 +02:00
Clifford Wolf
382cc90c65
Further improve extract_fa (seems to be fully functional now)
2017-08-25 13:41:54 +02:00
Clifford Wolf
0bf612506c
Rename "adders" to "extract_fa"
2017-08-25 12:04:40 +02:00
Clifford Wolf
15cdda7c4b
Towards more generic "adder" function extractor
2017-08-23 14:20:10 +02:00
Clifford Wolf
51cbec7f75
Add experimental adders pass
2017-08-22 13:52:13 +02:00
Clifford Wolf
df3e6e1ec9
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
Clifford Wolf
ca53fba44a
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
Clifford Wolf
d38a64b1cf
More intuitive handling of "cd .." for singleton modules
2017-08-19 00:15:12 +02:00
Clifford Wolf
bbdf7d9c66
Add "sim -zinit -rstlen"
2017-08-18 12:54:17 +02:00
Clifford Wolf
d30cc60ba9
Add "sim" support for memories
2017-08-18 11:44:50 +02:00
Clifford Wolf
0be738eaac
Add support for assert/assume/cover to "sim" command
2017-08-18 10:24:14 +02:00
Clifford Wolf
92e4b5aa77
Add writeback mode to "sim" command
2017-08-17 15:54:51 +02:00
Clifford Wolf
7b4f3f86c3
Improve "sim" command
2017-08-17 12:27:08 +02:00
Clifford Wolf
75046aa531
Add "sim" command skeleton
2017-08-16 13:05:21 +02:00
Clifford Wolf
88983f5012
Mostly coding style related fixes in rmports pass
2017-08-15 11:32:35 +02:00
Clifford Wolf
9fe6bc48a9
Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports
2017-08-15 11:19:55 +02:00
Robert Ou
9a64ba3338
abc: Allow +/ filenames in the abc command
2017-08-14 12:11:11 -07:00
Andrew Zonenberg
15e41d6363
rmports: Now remove ports from cell instances if we optimized them out of that cell
2017-08-14 11:44:05 -07:00
Andrew Zonenberg
0ee27d0226
ProcessModule is no longer virtual (why was it in the first place?)
2017-08-14 11:18:09 -07:00
Andrew Zonenberg
bd2ac68769
rmports now works on all modules in the design, not just the top.
2017-08-14 11:16:44 -07:00
Andrew Zonenberg
d5e5bbad86
Updated Makefile to reflect opt_rmports being renamed to rmports
2017-08-14 11:04:56 -07:00
Andrew Zonenberg
1a6a23f91a
Renamed opt_rmports pass to rmports
2017-08-14 11:00:45 -07:00
Andrew Zonenberg
1bb150c231
Improved handling of constant connections in opt_rmports
2017-08-14 10:28:19 -07:00
Andrew Zonenberg
2877d5e504
Fixed handling of cell ports that aren't wires
2017-08-14 10:28:16 -07:00
Andrew Zonenberg
3dd7f42e2b
opt_rmports: Fixed incorrect handling of multi-bit nets
2017-08-14 10:28:11 -07:00
Andrew Zonenberg
66aac06eee
Removed commented out debug code
2017-08-14 10:28:04 -07:00
Andrew Zonenberg
cca3cb5fbb
Added opt_rmports pass (remove unconnected ports from top-level modules)
2017-08-14 10:27:59 -07:00
Clifford Wolf
007f29b9c2
Add support for set-reset cell variants to opt_rmdff
2017-08-09 13:29:52 +02:00
Clifford Wolf
c4a7958f70
Add handling of constant reset signals to opt_rmdff
2017-08-06 13:27:18 +02:00
Clifford Wolf
5c09f24e48
Fix typo in "abc" pass help message
2017-07-29 16:21:58 +02:00
Clifford Wolf
e7d1277a2c
Add consolidation of init attributes to opt_clean, some opt_clean log fixes
2017-07-29 00:10:33 +02:00
Clifford Wolf
649bb9374f
Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators
2017-07-26 18:28:55 +02:00
Clifford Wolf
b6bd12fade
Add error for cell output ports that are connected to constants
2017-07-22 15:08:30 +02:00
Clifford Wolf
b3bc7068d1
Fix handling of empty cell port assignments (i.e. ignore them)
2017-07-21 19:32:31 +02:00
Clifford Wolf
c00d8a5b73
Add $alu to list of supported cells for "stat -width"
2017-07-14 11:32:49 +02:00
Salvador E. Tropea
ca23554528
Excluded $_TBUF_ from opt_merge pass
2017-07-03 13:21:20 -03:00
Clifford Wolf
0a02cdb93b
Fix and_or_buffer optimization in opt_expr for signed operators
2017-07-01 16:05:26 +02:00
Clifford Wolf
0f217080cf
Add "design -import"
2017-06-30 19:18:52 +02:00
Clifford Wolf
8952bd6f45
Add chtype command
2017-06-30 17:57:34 +02:00
Clifford Wolf
18c030a8c9
Add $tribuf to opt_merge blacklist
2017-06-30 17:44:44 +02:00
Clifford Wolf
155a80dfb7
Fix handling of init values in "abc -dff" and "abc -clk"
2017-06-20 15:32:23 +02:00
Clifford Wolf
f6421c83a2
Switched abc "clock domain not found" error to log_cmd_error()
2017-06-20 04:22:34 +02:00
Clifford Wolf
05df3dbee4
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
Clifford Wolf
9ed4c9d710
Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
Clifford Wolf
fad52abf70
Add aliases for common sets of gate types to "abc -g"
2017-05-24 11:39:05 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
3bbac5c141
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Clifford Wolf
dee4ec1661
Fix gcc compiler warning
2017-04-05 11:21:06 +02:00
Clifford Wolf
180d704568
Disable opt_merge for $anyseq and $anyconst
2017-02-28 22:17:00 +01:00
Clifford Wolf
1a6c02a532
Add "chformal -assert2assume" and friends
2017-02-28 00:00:44 +01:00
Clifford Wolf
db7fc0e32d
Add "chformal" pass
2017-02-27 13:25:28 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
cf25dc9ce7
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
Clifford Wolf
69468d5a16
Do not fix port widths on any blackbox instances
2017-02-13 17:07:38 +01:00
Clifford Wolf
db7314bc02
Fix techmap for inout ports connected to inout ports
2017-02-13 16:55:25 +01:00
Clifford Wolf
76c4ee096b
Do not eagerly fix port widths on parameterized cells
2017-02-12 17:42:57 +01:00
Clifford Wolf
95dae6d416
Fixed some "used uninitialized" warnings in opt_expr
2017-02-11 10:50:48 +01:00
Clifford Wolf
a5bfeb9e07
Add optimization of (a && 1'b1) and (a || 1'b0)
2017-02-11 10:05:00 +01:00
C-Elegans
94b272077d
Fix issue #306 , "Bug in opt -full"
...
Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0
2017-02-10 10:38:02 -05:00
Clifford Wolf
e6cc67b46f
Fix handling of init attributes with strange width
2017-02-09 16:06:58 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
8927e19b13
Update ABC scripts to use "&nf" instead of "map"
2017-02-01 11:15:20 +01:00
Clifford Wolf
ffbe8d41f3
Fix indenting and log messages in code merged from opt_compare_pr
2017-01-31 16:20:56 +01:00
Clifford Wolf
19a980277f
Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr
2017-01-31 15:54:41 +01:00
Clifford Wolf
7481ba4750
Improve opt_rmdff support for $dlatch cells
2017-01-31 10:15:04 +01:00
C-Elegans
a94c3694d7
Refactor and generalize the comparision optimization
...
Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a
2017-01-30 17:52:16 -05:00
Clifford Wolf
fe29869ec5
Add $ff and $_FF_ support to equiv_simple
2017-01-30 10:50:38 +01:00
Clifford Wolf
45e10c1c89
Be more conservative with merging large cells into FSMs
2017-01-26 09:19:28 +01:00
Clifford Wolf
49b8160488
Add warnings for quickly growing FSM table size in fsm_expand
2017-01-26 09:05:59 +01:00
C-Elegans
2fa0fd4a37
Do not use b.as_int() in calculation of bit set
2017-01-21 12:58:26 -05:00
C-Elegans
84f9cd0025
Optimize compares to powers of 2
...
Remove opt_compare and put comparison pass in opt_expr
assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a < (1<<x) becomes !a[7:x]
Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false
delete opt_compare.cc
revert opt.cc to commit b7cfb7dbd
(remove opt_compare step)
2017-01-16 13:45:50 -05:00
Austin Seipp
6781543244
passes/hierarchy: delete some dead code
...
Signed-off-by: Austin Seipp <aseipp@pobox.com>
2017-01-15 16:39:12 -06:00
C-Elegans
943389cdd5
Fix issue #269 , optimize signed compare with 0
...
add opt_compare pass and add it to opt
for a < 0:
if a is signed, replace with a[max_bit-1]
for a >= 0:
if a is signed, replace with ~a[max_bit-1]
2017-01-15 13:38:29 -05:00
Clifford Wolf
0cac95ea94
Added "check -initdrv"
2017-01-04 18:12:41 +01:00
Clifford Wolf
f0df7dd796
Added cell port resizing to hierarchy pass
2017-01-01 23:03:44 +01:00
Clifford Wolf
b1cdf772eb
Added "design -reset-vlog"
2016-11-30 11:25:55 +01:00
Clifford Wolf
ac7a175a3c
Improved equiv_purge log output
2016-11-29 13:30:35 +01:00
Clifford Wolf
e444e59963
Added wire start_offset and upto handling to splitnets cmd
2016-11-23 13:54:33 +01:00
Clifford Wolf
55785a96eb
Improved ABC default scripts
2016-11-19 18:20:54 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
1827a48964
Minor bugfix in submod
2016-11-09 13:13:26 +01:00
Clifford Wolf
97ac77513f
Bugfix in "setundef" pass
2016-11-08 18:53:36 +01:00
Clifford Wolf
ef603c6fe1
Implemented "scc -set_attr"
2016-11-06 00:04:10 +01:00
Clifford Wolf
914aa8a5d3
Bugfix in "scc" command
2016-11-06 00:03:35 +01:00
Clifford Wolf
308a4b4a1b
Bugfix in "hierarchy -check"
2016-11-02 20:09:57 +01:00
Clifford Wolf
b63cace90f
Added support for fsm_encoding="user"
2016-11-02 13:15:49 +01:00
Clifford Wolf
0c8e973d32
Added "fsm_expand -full"
2016-11-02 09:31:39 +01:00
Clifford Wolf
d9d38eeedb
Bugfix in fsm_map for FSMs without reset state
2016-10-25 23:21:37 +02:00
Clifford Wolf
aa72262330
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
Clifford Wolf
3655d7fea7
Added "setparam -type"
2016-10-19 13:54:04 +02:00
Clifford Wolf
15fb56697a
Bugfix in "miter -assert" handling of assumptions
2016-10-17 14:56:58 +02:00
Clifford Wolf
6425d34e73
Added clk2fflogic support for $dffsr and $dlatch
2016-10-17 13:28:55 +02:00
Clifford Wolf
3a09d6bb65
Improvements and bugfixes in clk2fflogic
2016-10-16 23:03:29 +02:00
Clifford Wolf
74702b04c2
Build fixes for VS 2015
2016-10-16 20:37:02 +02:00
Clifford Wolf
fa535c0b00
Some minor build fixes for Visual C
2016-10-14 18:36:02 +02:00
Clifford Wolf
e4c5ee9b89
Avoid using strcasecmp()
2016-10-14 18:20:36 +02:00
Clifford Wolf
2733994aeb
Added clk2fflogic
2016-10-14 14:55:07 +02:00
Clifford Wolf
2ef454c3f5
Added opt_rmdff support for $ff cells
2016-10-14 13:02:36 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
ffbb4e992e
Added MEMID handling to "flatten" pass
2016-10-14 10:36:37 +02:00
Clifford Wolf
ee91350add
Added "zinit" pass
2016-10-12 12:05:19 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
ed519f578e
Added "opt_rmdff -keepdc"
2016-09-30 17:02:38 +02:00
Clifford Wolf
e788ad4885
Cosmetic fix in test_autotb.cc
2016-09-19 20:43:43 +02:00
Clifford Wolf
5e155aa121
Avoid creating very long strings in test_autotb
2016-09-19 10:20:20 +02:00
Clifford Wolf
d8ad889594
Bugfix in techmap parameter handling
2016-09-14 20:46:54 +02:00
Kaj Tuomi
df4ab169a7
Typo fix.
2016-09-08 10:57:16 +03:00
Clifford Wolf
cb7dbf4070
Improvements in assertpmux
2016-09-07 12:42:16 +02:00
Clifford Wolf
ab18e9df7c
Added assertpmux
2016-09-07 00:28:01 +02:00
Clifford Wolf
f3f5a02045
Added "tee +INT -INT"
2016-09-06 17:43:24 +02:00
Clifford Wolf
fc5281b3f7
Run log_flush() before solving in sat command
2016-09-06 17:35:25 +02:00
Clifford Wolf
4ea7054b56
Improved init spec handling in opt_rmdff, modernized the code a bit
2016-08-30 01:34:04 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
66582964bc
Improved "show" help message
2016-08-28 12:34:36 +02:00
Clifford Wolf
23afeadb5e
Fixed handling of transparent bram rd ports on ROMs
2016-08-27 17:06:22 +02:00
Clifford Wolf
cad40fc874
Fixed bug in memory_share for memory ports with different ABITS
2016-08-22 14:26:33 +02:00
Clifford Wolf
d77a914683
Added "wreduce -memx"
2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453
Added memory_memx pass, "memory -memx", and "prep -memx"
2016-08-19 19:48:26 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
b3a01451a5
Bugfix in test_autotb
2016-08-18 13:43:12 +02:00
Clifford Wolf
00f29d5e5c
Fixed use-after-free dict<> usage pattern in hierarchy.cc
2016-08-16 09:07:13 +02:00
Clifford Wolf
321e15b0bf
Minor fixes in show command
2016-08-16 00:36:24 +02:00
Clifford Wolf
73b7232ec8
Fixed some compiler warnings in attrmap command
2016-08-10 13:44:08 +02:00
Clifford Wolf
b0aab4e304
Added "attrmap" command
2016-08-09 19:56:55 +02:00
Clifford Wolf
3c6d31fd06
Added "attrmvcp" pass
2016-08-09 11:18:48 +02:00
Clifford Wolf
9d15529214
Undo "preserve wire attributes in iopadmap" change (it was OK before)
2016-08-08 11:47:35 +02:00
Clifford Wolf
88a67afa7d
Added "test_autotb -seed" (and "autotest.sh -S")
2016-08-06 13:32:29 +02:00
Clifford Wolf
90c17aad56
preserve wire attributes in iopadmap
2016-08-06 13:24:59 +02:00
Clifford Wolf
5d6765a9d2
Added "insbuf" command
2016-08-02 10:37:19 +02:00
Clifford Wolf
8537c4d206
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
2016-07-25 16:39:25 +02:00
Clifford Wolf
b1c432af56
Improvements in CellEdgesDatabase
2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2
Added CellEdgesDatabase API
2016-07-24 13:59:57 +02:00
Clifford Wolf
54966679df
Moved SatHelper::setup_init() code to SatHelper::setup()
2016-07-24 12:18:39 +02:00
Clifford Wolf
34e833103b
Added $initstate support to "sat" command
2016-07-23 17:01:03 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
e92998a79c
Minor bugfix in FSM reset state detection
2016-07-12 09:46:15 +02:00
Clifford Wolf
b5a9fba0db
Further improved fsm_detect output, attempt to detect self-resetting circuits
2016-07-09 14:02:49 +02:00
Clifford Wolf
d63ffabacb
Added printing of some warning messages to fsm_detect
2016-07-09 13:23:06 +02:00
Clifford Wolf
6ed6b3cb6d
Replaced "select -assert-limit" with -assert-max and -assert-min
2016-07-01 12:24:13 +02:00
eshellko
9a742f4069
Added 'assert-limit' option for 'select' command
...
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
2016-07-01 10:24:22 +04:00
Clifford Wolf
541083cf32
Bugfix in "abc -script" handling
2016-06-19 22:19:19 +02:00
Clifford Wolf
ca91bccb6b
Added "deminout"
2016-06-19 13:08:16 +02:00
Clifford Wolf
3380281e15
Added "dc2" to default ABC scripts
2016-06-17 20:15:35 +02:00
Clifford Wolf
f498204ae4
Added "abc -I <num> -P <num>"
2016-06-17 19:39:35 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
c3365034e9
Updated ABC to hg rev b5df6e2b76f0
2016-06-17 11:16:31 +02:00
Clifford Wolf
99edf24966
Added "nlutmap -assert"
2016-06-09 11:47:41 +02:00
Clifford Wolf
2032e6d8e4
Added "proc_mux -ifx"
2016-06-06 17:15:50 +02:00
Clifford Wolf
dcf576641b
Added "setundef -init"
2016-06-03 11:38:31 +02:00
Clifford Wolf
d2695e2bfa
Fix all undef-muxes in dlatch input cone
2016-06-02 14:37:07 +02:00
Clifford Wolf
adfc80727c
Avoid creating undef-muxes when inferring latches in proc_dlatch
2016-06-01 13:25:06 +02:00
Clifford Wolf
11f7b8a2a1
Added opt_expr support for div/mod by power-of-two
2016-05-29 12:17:36 +02:00
Clifford Wolf
611f121cb9
Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop
2016-05-27 16:33:13 +02:00
Marcus Comstedt
e22e4d59b8
Made the expansion order of hierarchy deterministic
2016-05-22 16:41:26 +02:00
Clifford Wolf
1e227caf72
Improvements and fixes in autotest.sh script and test_autotb
2016-05-20 16:58:02 +02:00
Kaj Tuomi
8c3bc2ac0d
Close opened dump file.
2016-05-19 11:53:29 +03:00
Kaj Tuomi
f6221ade95
Fix for Modelsim transcript line warp issue #164
2016-05-19 11:34:38 +03:00
Clifford Wolf
ffcdc53a18
Don't sign-extend memory bram initialization data
2016-05-15 00:05:30 +02:00
Clifford Wolf
c3f6e0ea85
Added support for "keep" attribute to shregmap
2016-05-07 09:33:16 +02:00
Clifford Wolf
aadca148da
Fixed preservation of important attributes in techmap
2016-05-06 13:59:30 +02:00
Andrew Zonenberg
3486637b19
Changed port names in greenpak shregmap
2016-05-04 17:04:50 -07:00
Clifford Wolf
9647dc3c07
Added tristate buffer support to iopadmap
2016-05-04 22:48:02 +02:00
Clifford Wolf
658f93663b
Fixed iopadmap attribute handling
2016-05-04 10:48:23 +02:00
Clifford Wolf
e01464e2ac
Added "qwp -v"
2016-04-28 23:17:30 +02:00
Clifford Wolf
0d2923cccd
Connections between inputs and inouts are driven by the input
2016-04-26 19:49:05 +02:00
Clifford Wolf
958fb29c76
Fixed test_autotb for modules with many cell ports
2016-04-25 16:37:11 +02:00
Clifford Wolf
93e107e455
Fixed proc_mux performance bug
2016-04-25 10:43:04 +02:00
Clifford Wolf
b1d6f05fa2
Fixed performance bug in proc_dlatch
2016-04-24 19:29:56 +02:00
Clifford Wolf
096c25d29d
Improvements in greenpak4 shreg mapping
2016-04-23 23:10:13 +02:00
Andrew Zonenberg
7f16784f3c
Merge https://github.com/cliffordwolf/yosys
2016-04-23 12:22:08 -07:00
Clifford Wolf
e13c66122e
Added "shregmap -zinit" for greenpak4 tech
2016-04-23 20:20:21 +02:00
Andrew Zonenberg
2849fd486e
Fixed typo in help text
2016-04-22 23:01:39 -07:00
Clifford Wolf
7311be4028
Added "shregmap -tech greenpak4"
2016-04-22 19:42:08 +02:00
Clifford Wolf
965b0d59b5
More flexible handling of initialization values
2016-04-22 12:13:06 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
1565d1af69
Fixed performance bug in "share" pass
2016-04-21 19:47:25 +02:00
Clifford Wolf
f38ca3e18f
Improvements in opt_expr
2016-04-21 14:23:04 +02:00
Clifford Wolf
1761d08dd2
Bugfix and improvements in memory_share
2016-04-21 14:22:58 +02:00
Clifford Wolf
f1fa757d0e
Added "shregmap -params"
2016-04-18 11:58:21 +02:00
Clifford Wolf
525651c8f6
Added "shregmap -zinit" and "shregmap -init"
2016-04-18 11:44:10 +02:00
Clifford Wolf
ce7c980ec7
Improvements in "shregmap"
2016-04-17 15:37:22 +02:00
Clifford Wolf
de647a390c
Added "shregmap" pass
2016-04-16 23:20:49 +02:00
Clifford Wolf
fbdb8e7b3e
Fixed copy&paste error in log message in lut2mux
2016-04-16 23:20:34 +02:00
Clifford Wolf
6041f780c3
Prefer noninverting FFs in dfflibmap
2016-04-05 12:51:04 +02:00
Clifford Wolf
eaac5bfbc7
Improved formatting of "sat" output tables
2016-04-05 08:26:10 +02:00
Clifford Wolf
6cafd08ac1
Improved opt_merge support for $pmux cells
2016-03-31 09:58:55 +02:00
Clifford Wolf
e5dd5c0bcc
Preserve empty $pmux default cases
2016-03-31 09:57:23 +02:00
Clifford Wolf
e2f6d61c00
Typo fixes in opt_expr and opt_merge
2016-03-31 09:56:56 +02:00
Clifford Wolf
ec93680bd5
Renamed opt_share to opt_merge
2016-03-31 08:52:49 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Andrew Zonenberg
984561c034
Renamed counters pass to greenpak4_counters
2016-03-30 22:52:01 -07:00
Andrew Zonenberg
1ae33344f4
Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now.
2016-03-30 22:40:14 -07:00
Andrew Zonenberg
1b42e0c471
Reduced log verbosity
2016-03-30 22:03:50 -07:00
Andrew Zonenberg
ad19e0c64a
Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros.
2016-03-30 21:54:23 -07:00
Andrew Zonenberg
d16d05e415
Merge https://github.com/cliffordwolf/yosys
2016-03-30 20:38:18 -07:00
Andrew Zonenberg
dd7204c0bd
Fixed typo in log message
2016-03-30 20:30:03 -07:00
Andrew Zonenberg
489caf32c5
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
2016-03-30 01:07:20 -07:00
Clifford Wolf
a47f69536a
Added support for installed plugins
2016-03-30 10:02:03 +02:00
Clifford Wolf
9717495401
Fixed handling of inverters (aka 1-input luts) in nlutmap
2016-03-23 08:56:08 +01:00
Clifford Wolf
043fa0fad0
Cleanup abstract modules at end of "hierarchy -top"
2016-03-21 16:37:35 +01:00
Clifford Wolf
2c7e107d7a
Support for abstract modules in chparam
2016-03-21 16:37:35 +01:00
Clifford Wolf
bb9374b67c
Improvements in ABCEXTERNAL handling
2016-03-19 20:02:40 +01:00
Sergey Kvachonok
2656b2c55a
Support calling out to an external ABC.
...
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install
configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
2016-03-19 18:36:18 +03:00
Clifford Wolf
c4aaed099f
Using "mfs" and "lutpack" in ABC lut mapping
2016-03-07 11:14:11 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
0d7fd2585e
Added "int ceil_log2(int)" function
2016-02-13 16:52:16 +01:00
Clifford Wolf
825b99efc1
Added "stat -liberty" for calculating chip area
2016-02-04 12:26:13 +01:00
Clifford Wolf
801c022457
Improved dffsr2dff pass
2016-02-02 19:42:49 +01:00
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
Clifford Wolf
d6592d5b99
Use alphanumerical order instead of idstring idx in opt_clean compare_signals()
2016-02-02 09:16:18 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
9251553592
Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)
2016-02-01 11:49:11 +01:00
Clifford Wolf
71f418c468
More clang sanitizer stuff
2016-01-31 19:55:48 +01:00
Clifford Wolf
8b3f8cd220
Added "equiv_struct -fwonly"
2016-01-08 10:59:16 +01:00
Clifford Wolf
f5008f4f8a
Bugfixes in equiv_struct
2016-01-08 09:57:28 +01:00
Clifford Wolf
d00c63c927
Added "submod -copy"
2016-01-08 09:08:12 +01:00
Clifford Wolf
c3fd03d722
Added "equiv_struct -maxiter <N>"
2016-01-06 13:54:54 +01:00
Clifford Wolf
1f8c47fb47
Added "equiv_add -try" mode
2016-01-06 13:54:00 +01:00
Clifford Wolf
1d62f8710f
Fixed "splitnets -ports" for hierarchical designs
2015-12-22 13:25:00 +01:00
Clifford Wolf
ab0c44d3ed
Added %R select expression
2015-12-20 13:35:58 +01:00
Clifford Wolf
1ea6db3db8
Improved proc_mux performance for huge always blocks
2015-12-02 22:02:20 +01:00
Clifford Wolf
e61c7f887a
Added torder command
2015-11-19 15:34:32 +01:00
Clifford Wolf
d98d99aec6
Added "abc -g"
2015-11-10 11:10:11 +01:00
Marcus Comstedt
8c2bdef36d
Fix a segfault in dffinit when the value has too few bits
...
The code was already trying to add the required number of bits, but
fell one short of the mark.
2015-11-08 19:16:56 +01:00
Clifford Wolf
1ec6429bad
Added "singleton" pass
2015-11-07 19:10:43 +01:00
Clifford Wolf
f401eeb0cf
Bugfix in mapping $tribuf to $_TBUF_
2015-11-05 12:37:43 +01:00
Clifford Wolf
ddf3e2dc65
Bugfix in memory_dff
2015-10-31 22:01:41 +01:00
Clifford Wolf
ccdbf41be6
Improvements in wreduce
2015-10-31 13:39:30 +01:00
Clifford Wolf
0c202a2549
Use mfp<> in equiv_mark
2015-10-27 19:15:35 +01:00
Clifford Wolf
27714acd8a
Improvements in equiv_struct
2015-10-25 22:04:20 +01:00
Clifford Wolf
d014ba2d0e
Major refactoring of equiv_struct
2015-10-25 19:31:29 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
da923c198e
Added "equiv_add -cell"
2015-10-25 14:35:40 +01:00
Clifford Wolf
83bd27bf6e
equiv_struct now creates equiv_merged attributes
2015-10-25 02:15:20 +02:00
Clifford Wolf
453736d918
Improvements in equiv_struct
2015-10-24 23:04:17 +02:00
Clifford Wolf
7f110e7018
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
2015-10-24 22:56:40 +02:00
Clifford Wolf
6af8076967
improvement in "stat"
2015-10-24 21:56:53 +02:00
Clifford Wolf
6fe48cf41e
equiv_purge bugfix, using SigChunk in Yosys namespace
2015-10-24 19:09:45 +02:00
Clifford Wolf
2a0f577f83
Fixed handling of driver-driver conflicts in wreduce
2015-10-24 13:44:35 +02:00
Clifford Wolf
4cec1c058d
Added equiv_mark command
2015-10-23 23:56:58 +02:00
Clifford Wolf
c35db8c19e
Disabled "Skipping blackbox module" msg in show command
2015-10-23 20:11:05 +02:00
Clifford Wolf
15a67392f1
Also merge $equiv cells in equiv_struct
2015-10-23 15:26:58 +02:00
Clifford Wolf
d19069b0fb
Improvements in equiv_struct
2015-10-23 15:11:57 +02:00
Clifford Wolf
84a07ffb8a
Added equiv_purge
2015-10-22 15:40:27 +02:00
Clifford Wolf
00e05b1310
Added equiv_struct command
2015-10-21 17:12:35 +02:00
Clifford Wolf
6416dfee93
Improved inout handling in equiv_make
2015-10-21 15:42:50 +02:00
Clifford Wolf
1d83854d84
Bugfixes in handling of "keep" attribute on wires
2015-10-15 14:57:28 +02:00
Clifford Wolf
eb1e3caae7
Fixed "flatten" for unconnected inout ports
2015-10-13 10:30:23 +02:00
Clifford Wolf
c58bd5dc30
Added edgetypes command
2015-09-27 11:53:20 +02:00
Clifford Wolf
281c1f4029
Some cleanups in qwp
2015-09-26 10:42:27 +02:00
Clifford Wolf
ddcfc99f8c
Added "test_cell -noeval"
2015-09-25 17:27:18 +02:00
Clifford Wolf
82028c42e0
Added wreduce $mul support and fixed signed $mul opt_const bug
2015-09-25 17:27:06 +02:00
Clifford Wolf
4864736167
Bugfix in bram read-enable code
2015-09-25 14:22:33 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
ec92c89659
Added pivoting to qwp solver
2015-09-24 22:16:37 +02:00
Clifford Wolf
69071bbc5f
Improved qwp performance
2015-09-24 21:50:37 +02:00
Clifford Wolf
b1e9cb332d
Added statistics summary to "qwp"
2015-09-24 21:22:24 +02:00
Clifford Wolf
3501f8e364
Fixed memory_bram for ROMs in BRAMs with write-enable inputs
2015-09-24 11:37:15 +02:00
Clifford Wolf
b66bf8bed1
Do not detect fsm state registers with init attribute
2015-09-21 11:54:00 +02:00
Clifford Wolf
11c27b5e69
Bugfix in "qwp" pass
2015-09-21 10:37:24 +02:00
Clifford Wolf
80898dcbc8
Improvements and fixes in "qwp" pass
2015-09-21 01:05:13 +02:00
Clifford Wolf
6329bea873
Added "qwp -dump"
2015-09-20 22:36:35 +02:00
Clifford Wolf
539c5eeb0f
Added "qwp" command
2015-09-20 18:28:46 +02:00
Clifford Wolf
598a475724
Added nlutmap
2015-09-18 21:57:34 +02:00
Clifford Wolf
c851f51656
Added lut2mux pass
2015-09-18 21:55:48 +02:00
Clifford Wolf
db548800b6
Added buffer detection to "abc -lut"
2015-09-18 20:12:56 +02:00
Clifford Wolf
452d4bf741
Added support for "dfflibmap -liberty +/..."
2015-09-18 11:55:57 +02:00
Clifford Wolf
51e1295d79
Added detection of "mux inverter" chains in opt_const
2015-09-18 11:55:31 +02:00
Clifford Wolf
b7535a6c75
Added $logic_not handling to fsm_detect
2015-09-18 10:46:50 +02:00
Clifford Wolf
e7c018e5d1
Fixed sharing of $memrd cells
2015-09-12 16:01:20 +02:00
Clifford Wolf
6f9a6fd783
Fixed port ordering in "splitnets" cmd
2015-09-01 13:10:36 +02:00
Clifford Wolf
b10ea0550d
gcc-4.6 build fixes
2015-09-01 12:51:23 +02:00
Clifford Wolf
24e7cf89bc
Fixed iopadmap help message
2015-08-31 16:49:42 +02:00
Clifford Wolf
92dce21f6e
Using dict<> and pool<> in alumacc pass
2015-08-31 16:26:01 +02:00
Clifford Wolf
f40d1b78b6
Added sat -show-regs, -show-public, -show-all
2015-08-18 17:14:30 +02:00
Clifford Wolf
246e362717
Bugfix in fsm_detect for complex muxtrees
2015-08-18 14:17:50 +02:00
Clifford Wolf
f43815054e
Properly clean up unused "init" attributes
2015-08-18 13:50:15 +02:00
Clifford Wolf
9c33172ece
Added tribuf command
2015-08-16 12:55:25 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Clifford Wolf
ae09c89f62
Fixed opt_clean handling of inout ports
2015-08-16 09:50:17 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Larry Doolittle
022f570563
Keep gcc from complaining about uninitialized variables
2015-08-14 23:26:49 +02:00
Clifford Wolf
0350074819
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
80910d13a6
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 09:52:06 +02:00
Clifford Wolf
08ad5409a2
Some ASCII encoding fixes (comments and docs) by Larry Doolittle
2015-08-13 09:30:20 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
c43f38c81b
Improved handling of "keep" attributes in hierarchical designs in opt_clean
2015-08-12 14:10:14 +02:00
Clifford Wolf
667b015018
Merge pull request #70 from gaomy3832/bugfix
...
Remove unused blackbox modules in opt_clean.
2015-08-12 08:45:04 +02:00
Mingyu Gao
cbda56d178
Remove unused blackbox modules in opt_clean.
2015-08-11 09:51:08 -07:00
Mingyu Gao
8c4c62f3e1
Bugfix for cell hash cache option in opt_share.
2015-08-11 11:40:23 +02:00
Clifford Wolf
2185125760
Added missing ct_all setup to opt_clean
2015-08-11 07:54:32 +02:00
Mingyu Gao
021b4a2436
Bugfix for cell hash cache option in opt_share.
2015-08-10 13:01:44 -07:00
Clifford Wolf
883e09d8ed
Use MEMID as name for $mem cell
2015-08-09 13:35:44 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
3860c9a9f2
Fixed flatten $meminit handling
2015-07-30 21:43:41 +02:00
Clifford Wolf
4d0ba9b3b2
Fixed "check" command for inout ports
2015-07-27 09:54:58 +02:00
Clifford Wolf
2a613b1b66
Some cleanups in opt_rmdff
2015-07-25 12:09:57 +02:00
Clifford Wolf
badc5f7eb9
Added "miter -assert"
2015-07-25 12:09:57 +02:00
Clifford Wolf
2397078485
Keep modules with $assume (like $assert)
2015-07-25 12:09:57 +02:00
Clifford Wolf
914ae3401e
Improved $adff simplification
2015-07-24 14:12:50 +02:00
Clifford Wolf
ad919ae4e3
Fixed techmap processes error msg
2015-07-18 12:16:27 +02:00
Clifford Wolf
8393f70538
Some fixes in "select" command
2015-07-16 22:10:26 +02:00
Clifford Wolf
d2ff5d9994
Do not collect disabled $memwr cells
2015-07-06 13:28:00 +02:00
Clifford Wolf
766dd51447
Bugfix in fsm_extract
2015-07-03 18:42:36 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
053058d781
Added opt_const -clkinv
2015-07-01 10:49:21 +02:00
Clifford Wolf
ee9188a5b4
Added logic-loop error handling to freduce
2015-06-30 17:11:46 +02:00
Clifford Wolf
77e89399a6
Bugfix in chparam
2015-06-30 01:38:34 +02:00
Clifford Wolf
caa274ada6
Added design->rename(module, new_name)
2015-06-30 01:37:59 +02:00
Clifford Wolf
99100f367d
Added "rename -top new_name"
2015-06-17 09:38:56 +02:00
Clifford Wolf
66910e15b2
Modernized memory_dff (and fixed a bug)
2015-06-14 16:15:51 +02:00
Clifford Wolf
f6eca509bb
Added "memory -nordff"
2015-06-14 15:47:11 +02:00
Clifford Wolf
4c733301e6
Fixed cstr_buf for std::string with small string optimization
2015-06-11 13:39:49 +02:00
Clifford Wolf
1ae360cf72
AigMaker refactoring
2015-06-10 23:00:12 +02:00
Clifford Wolf
56d4822719
Renamed "aig" to "aigmap"
2015-06-10 07:24:26 +02:00
Clifford Wolf
85287295b2
Fixed cellaigs port extending
2015-06-10 07:16:30 +02:00
Clifford Wolf
66f9ee412a
Added "aig" pass
2015-06-09 22:33:26 +02:00
Clifford Wolf
b57cb4a7fe
Merge clock inverters in memory_dff
2015-06-09 07:25:12 +02:00
Clifford Wolf
08f9b38a9c
Added opt_share -share_all
2015-05-31 14:24:34 +02:00
Clifford Wolf
522705cc28
Added liberty dont_use support to dfflibmap
2015-05-31 07:51:12 +02:00
Clifford Wolf
9f772eb970
Improved "flatten" handlings of inout ports
2015-05-23 10:14:53 +02:00
Clifford Wolf
4b6221478e
Added simple $dlatch support to opt_rmdff
2015-05-23 09:45:48 +02:00
Clifford Wolf
e122c2644e
preserve used $-wires with init attribute in opt_clean
2015-05-22 08:20:29 +02:00
Clifford Wolf
e5116eeb77
Generalized blifparse API
2015-05-17 15:10:37 +02:00
Clifford Wolf
7dad017c9c
abc/blifparse files reorganization
2015-05-17 14:44:28 +02:00
Clifford Wolf
c2f30e0de4
Added .barbuf support to abc BLIF parser
2015-05-13 06:45:12 +02:00
Clifford Wolf
7462618591
Fixed memory_unpack for initialized memories
2015-04-29 19:55:32 +02:00
Clifford Wolf
96be31de89
Preserve important attributes in splitnets
2015-04-29 07:44:57 +02:00
Clifford Wolf
f483dce7c2
Added $eq/$neq -> $logic_not/$reduce_bool optimization
2015-04-29 07:28:15 +02:00
Clifford Wolf
794d22969d
Added simplemap $lut support
2015-04-27 10:16:07 +02:00
Clifford Wolf
49859393bb
Improved attributes API and handling of "src" attributes
2015-04-24 22:04:05 +02:00
Clifford Wolf
11f77205f5
Fixed memory_share for unconditional write with part select to memory
2015-04-22 06:40:23 +02:00
Clifford Wolf
faa95dd845
don't consider blackbox modules in "sat" command
2015-04-18 09:29:03 +02:00
Clifford Wolf
9041f34233
Improved handling of init values in opt_rmdff
...
based on a patch by Mingyu Gao, user gaomy3832 on github
2015-04-18 08:04:31 +02:00
Clifford Wolf
8cdbcf6859
Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
2015-04-17 21:35:59 +02:00
Clifford Wolf
e050467b89
Improved "maccmap" help message
2015-04-16 18:23:43 +02:00
Clifford Wolf
dc30b034f7
Fixed "dff2dffe -direct-match"
2015-04-16 11:47:59 +02:00
Clifford Wolf
f80d020f17
Added "dff2dffe -direct-match"
2015-04-16 11:30:17 +02:00
Clifford Wolf
2fc2f8f5b3
Added "splice -wires"
2015-04-13 19:28:12 +02:00
Clifford Wolf
e305d85807
Added handling of bool-output cells to "wreduce"
2015-04-13 19:27:49 +02:00
Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
Clifford Wolf
d176e613c2
Minor fixes in handling of "init" attribute
2015-04-09 15:12:26 +02:00
Clifford Wolf
be7b9b34ca
techmap code cleanup
2015-04-09 12:02:26 +02:00
Clifford Wolf
21a1cc1b60
Added support for "file names with blanks"
2015-04-08 12:14:34 +02:00
Clifford Wolf
aa0ab975b9
Removed "techmap -share_map" (use "-map +/filename" instead)
2015-04-08 12:13:53 +02:00
Clifford Wolf
8eadd8fb18
Added %M and %C select operators
2015-04-07 22:22:09 +02:00
Clifford Wolf
724cead61d
Added "pmuxtree" command
2015-04-07 20:27:10 +02:00
Clifford Wolf
1f33b2a490
Added "chparam -list"
2015-04-07 19:21:30 +02:00
Clifford Wolf
590f74d8f0
Added decoder generation to "muxcover"
2015-04-07 18:03:27 +02:00
Clifford Wolf
f7fb21f185
Added "muxcover" command
2015-04-07 15:42:25 +02:00
Clifford Wolf
c1af590f4e
typo fix
2015-04-07 07:43:01 +02:00
Clifford Wolf
329b841aac
Added "chparam" command
2015-04-07 07:30:14 +02:00
Clifford Wolf
169d1c4711
Added support for initialized brams
2015-04-06 17:06:15 +02:00
Clifford Wolf
a1c62b79d5
Avoid parameter values with size 0 ($mem cells)
2015-04-05 18:04:19 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
4b44907619
documentation improvements
2015-03-29 20:22:08 +02:00
Clifford Wolf
68bbb15214
Fixed detection of absolute paths in ABC for win32
2015-03-22 11:03:56 +01:00
Clifford Wolf
8b1e0bdd9e
Fixed handling of quotes in liberty parser
2015-03-18 16:03:19 +01:00
Clifford Wolf
aed4d763cf
Added hierarchy -auto-top
2015-03-18 08:33:40 +01:00
Clifford Wolf
ed15400fc6
Fixed bug in "hierarchy" for parametric designs
2015-03-04 15:52:34 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
27a918eadf
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-25 23:01:54 +01:00
Clifford Wolf
331f8b8d0b
Bugfix in iopadmap
2015-02-25 23:01:42 +01:00
Clifford Wolf
3fe18c26cd
Added "keep_hierarchy" attribute
2015-02-25 12:46:00 +01:00
Clifford Wolf
9ae21263f0
Some cleanups in "clean"
2015-02-24 22:31:30 +01:00
Clifford Wolf
81fa4e81a6
Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.
...
(original patch by Andrew Becker <andrew.becker@epfl.ch>)
2015-02-24 11:01:00 +01:00
Clifford Wolf
c4f383e452
Fixed "check -assert"
2015-02-22 16:29:44 +01:00
Clifford Wolf
d361d313e1
Added "check -assert" doc
2015-02-22 13:02:48 +01:00
Clifford Wolf
e8307cefd9
Added "check -assert"
2015-02-22 13:00:41 +01:00
Clifford Wolf
39d25b212c
Fixed "sat -initsteps" off-by-one bug
2015-02-22 12:42:05 +01:00
Clifford Wolf
fae0e75ace
Added "sat -stepsize" and "sat -tempinduct-step"
2015-02-21 22:52:49 +01:00
Clifford Wolf
b19c926af8
sat docu change
2015-02-21 22:03:54 +01:00
Clifford Wolf
9237fb924e
When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
2015-02-21 20:05:16 +01:00
Clifford Wolf
1688b9b464
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
2015-02-21 17:53:22 +01:00
Clifford Wolf
dcbd00c101
Fixed basecase init for "sat -tempinduct"
2015-02-21 17:43:49 +01:00
Clifford Wolf
49dd9c713f
Fixed "flatten" for non-pre-derived modules
2015-02-21 15:01:13 +01:00
Clifford Wolf
4e6ca7760f
Replaced ezDefaultSAT with ezSatPtr
2015-02-21 12:15:41 +01:00
Clifford Wolf
f778a4081c
Catch constants assigned to cell outputs in "flatten"
2015-02-21 11:21:28 +01:00
Clifford Wolf
08c0fe164f
format fixes in "sat -dump_json"
2015-02-19 13:19:04 +01:00
Clifford Wolf
1ecee6c49c
Added "sat -dump_json" (WaveJSON format)
2015-02-19 10:53:40 +01:00
Clifford Wolf
20eb5cad4b
Changed "show" defaults for Win32
2015-02-19 09:11:38 +01:00
Clifford Wolf
f41378af8c
Fixed clang (svn trunk) warnings
2015-02-18 14:54:22 +01:00
Clifford Wolf
e4cf604ffd
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-18 07:19:03 +01:00
Clifford Wolf
5f54be54b8
Added "select %xe %cie %coe"
2015-02-18 07:18:34 +01:00
Clifford Wolf
024aa559e2
wreduce help typo fix
2015-02-17 13:02:16 +01:00
Clifford Wolf
0748ef638d
Bugfix in wreduce
2015-02-16 09:08:00 +01:00
Clifford Wolf
0283703f9e
Added Viz to yosys.js
2015-02-15 22:53:41 +01:00
Clifford Wolf
40f021e136
Added "check -noinit"
2015-02-15 12:58:12 +01:00
Clifford Wolf
a54c994e2b
Cosmetic fixes in "hierarchy" for blackbox modules
2015-02-15 12:57:41 +01:00
Clifford Wolf
3216f9420e
More emscripten stuff, Added example app
2015-02-15 12:09:30 +01:00
Clifford Wolf
c6ae9ebb79
Fixed "stat" handling of blackbox modules
2015-02-14 22:36:34 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
a0a0594d1e
hotfix in "check" command
2015-02-13 14:40:49 +01:00
Clifford Wolf
04cb947d6a
Added "check" command
2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
554a8df5e2
Added "proc_dlatch"
2015-02-12 16:56:01 +01:00
Clifford Wolf
87819c62fa
Less aggressive "share" defaults
2015-02-10 20:51:37 +01:00
Clifford Wolf
510deb3577
Added "scc -expect <N> -nofeedback"
2015-02-10 08:48:55 +01:00
Clifford Wolf
f889e3d385
Fixed iterator invalidation bug in "rename" command
2015-02-09 00:18:36 +01:00
Clifford Wolf
07afb14318
Fixed bug in "show -format .."
2015-02-08 23:29:54 +01:00
Clifford Wolf
bcd8a2fc56
Fixed eval_select_op() api
2015-02-08 19:06:16 +01:00
Clifford Wolf
09ee65a050
Added eval_select_args() and eval_select_op()
2015-02-08 18:56:06 +01:00
Clifford Wolf
5170b86108
Added equiv_add
2015-02-08 11:59:38 +01:00
Clifford Wolf
d5e30978e9
Added "select -read"
2015-02-06 10:01:22 +01:00
Clifford Wolf
a038787c9b
Added onehot attribute
2015-02-04 18:52:54 +01:00
Clifford Wolf
8805c24640
Fixed opt_clean performance bug
2015-02-04 16:34:06 +01:00
Clifford Wolf
a8f4a099b5
Using design->selected_modules() in opt_*
2015-02-03 23:45:01 +01:00
Clifford Wolf
6eb34038f4
Merge pull request #48 from rubund/master
...
Fixed typos found by lintian
2015-02-01 22:55:52 +01:00
Clifford Wolf
893fe87a33
Improved performance in equiv_simple
2015-02-01 22:50:48 +01:00
Ruben Undheim
49649d6ef0
Fixed typos found by lintian
2015-02-01 21:49:55 +01:00
Clifford Wolf
9abbeefe6e
Using selections in "ls" command
2015-02-01 00:13:19 +01:00
Clifford Wolf
8dfa105255
Bugfix in opt_const $eq -> buffer code
2015-01-31 23:25:32 +01:00
Clifford Wolf
1d92915a55
Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")
2015-01-31 21:07:42 +01:00
Clifford Wolf
bc86b4a7e9
Added "equiv_induct -undef"
2015-01-31 13:58:04 +01:00
Clifford Wolf
e9cfc4a453
Added "equiv_simple -undef"
2015-01-31 13:06:41 +01:00
Clifford Wolf
f80f5b721d
Added "equiv_make -blacklist <file> -encfile <file>"
2015-01-31 12:08:20 +01:00
Clifford Wolf
bedd46338f
Added "fsm -encfile"
2015-01-30 22:46:53 +01:00
Clifford Wolf
9ebf803cbe
Improved an error message
2015-01-28 00:46:00 +01:00
Clifford Wolf
df64542288
Fixed bug in equiv_miter
2015-01-28 00:34:30 +01:00
Clifford Wolf
23e54bda81
Added "sat -show-ports"
2015-01-27 23:04:28 +00:00
Clifford Wolf
13b50bacfe
Rethrow with "catch(...) throw;"
2015-01-25 22:57:09 +01:00
Clifford Wolf
acfaeb8d34
Added equiv_remove
2015-01-25 14:20:22 +01:00
Clifford Wolf
66a6b86daa
Added equiv_miter
2015-01-25 14:00:49 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
75bbeb828a
Various equiv_* improvements
2015-01-24 00:32:24 +01:00
Clifford Wolf
43951099cf
Added dict/pool.sort()
2015-01-24 00:13:27 +01:00
Clifford Wolf
1cb4c925d0
Improvements in equiv_make, equiv_induct
2015-01-22 21:23:01 +01:00
Clifford Wolf
5707ba22c1
Improved xdot calling
2015-01-22 20:45:53 +01:00
Clifford Wolf
f6d94e8720
Added equiv_induct
2015-01-22 14:03:18 +01:00
Clifford Wolf
a6aa32e762
Various equiv_simple improvements
2015-01-22 13:42:04 +01:00
Clifford Wolf
0a225f8b27
Moved equiv stuff to passes/equiv/
2015-01-22 12:03:15 +01:00
Clifford Wolf
abf8398216
Progress in equiv_simple
2015-01-21 23:59:58 +00:00
Clifford Wolf
74e1de1fac
Fixed opt_muxtree performance bug
2015-01-21 16:44:07 +01:00
Clifford Wolf
5febbe3620
Added equiv_simple
2015-01-19 15:08:44 +01:00
Clifford Wolf
615c2e136e
Added equiv_status
2015-01-19 14:20:04 +01:00
Clifford Wolf
76c5d863c5
Added equiv_make command
2015-01-19 13:59:08 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
f630868bc9
Improvements in opt_muxtree
2015-01-18 12:57:36 +01:00
Clifford Wolf
d3b35017f8
More opt_muxtree cleanups
2015-01-18 12:13:18 +01:00
Clifford Wolf
61192514e3
Various cleanups and improvements in opt_muxtree
2015-01-18 11:17:56 +01:00
Clifford Wolf
8658eed52a
Added support for memories to flatten (techmap)
2015-01-17 20:46:52 +01:00
Clifford Wolf
a95c229e12
Fixed a bug in opt_muxtree for "mux forests"
2015-01-17 13:56:53 +01:00
Clifford Wolf
3628ca989c
Improved opt_muxtree
2015-01-17 12:05:19 +01:00
Clifford Wolf
8ce8a230f4
Bugfix in dff2dffe
2015-01-16 17:51:17 +01:00
Clifford Wolf
2e36faeced
Added "abc -lut w1:w2"
2015-01-15 13:37:48 +01:00
Clifford Wolf
9065fb25cc
Fixed handling of foo.__TECHMAP_...
2015-01-15 13:36:57 +01:00
Clifford Wolf
8426884b40
Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)
2015-01-13 13:20:09 +01:00
Clifford Wolf
95f1eb9b87
Only enable code coverage counters on linux
2015-01-09 17:32:53 +01:00
Clifford Wolf
fd787609aa
disabled problematic mux -> and/or transform
2015-01-07 23:25:51 +01:00
Clifford Wolf
b26590f8ab
memory_bram hotfix for memories with width 1
2015-01-06 23:59:53 +01:00
Clifford Wolf
da72050107
removed old debug code
2015-01-06 16:08:04 +01:00
Clifford Wolf
9474928672
Towards Xilinx bram support
2015-01-06 15:26:33 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
081e1a49f8
Towards Xilinx bram support
2015-01-06 14:26:51 +01:00
Clifford Wolf
462b22f44f
dict<> ref vs insert bugfix
2015-01-06 00:16:44 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b
Towards Xilinx bram support
2015-01-04 14:23:30 +01:00
Clifford Wolf
daae35319b
Added memory_bram "shuffle_enable" feature
2015-01-04 13:14:30 +01:00
Clifford Wolf
5d631f0ea7
Removed left over debug code from memory_bram
2015-01-04 11:46:04 +01:00
Clifford Wolf
0648e2874c
Fixed pattern matching in "hierarchy -generate"
2015-01-04 11:45:39 +01:00
Clifford Wolf
45918b8315
Added "memory -bram"
2015-01-03 17:40:20 +01:00
Clifford Wolf
a7fe87f888
Added memory_bram 'or_next_if_better' feature
2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04
memory_bram transp support
2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
bbf89c4dc6
Progress in memory_bram
2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede
Progress in memory_bram
2015-01-02 00:07:44 +01:00
Clifford Wolf
f29f4e7c83
Progress in memory_bram
2015-01-01 15:32:37 +01:00
Clifford Wolf
17c1c55473
Progress in memory_bram
2015-01-01 12:17:19 +01:00
Clifford Wolf
e62d838bd4
Removed SigSpec::extend_xx() api
2015-01-01 11:41:52 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
11c3b81c08
typo fix for "opt -fast"
2014-12-30 22:35:38 +01:00
Clifford Wolf
972faab1c8
Fixed a bug in "select %ci %co %x"
2014-12-30 20:15:18 +01:00
Clifford Wolf
4606addfef
Fixed typo in ABC command
2014-12-30 19:38:40 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
ed8f1b42fc
Fixed memory corruption in "splice" command
2014-12-29 20:23:22 +01:00
Clifford Wolf
29a555ec7e
Added statehash to ezSAT
2014-12-29 17:10:37 +01:00
Clifford Wolf
7a4d5d1c0f
Less verbose ABC output
2014-12-29 15:17:40 +01:00
Clifford Wolf
3ff0d04555
Cleanups in opt_clean
2014-12-29 05:11:06 +01:00
Clifford Wolf
7d843adef9
dict/pool changes in opt_clean
2014-12-29 04:06:52 +01:00
Clifford Wolf
cfe0817697
Converting "share" to dict<> and pool<> complete
2014-12-29 02:01:42 +01:00
Clifford Wolf
9ff3a9f30d
Switched most of "share" to dict<> and pool<>
2014-12-29 00:42:48 +01:00
Clifford Wolf
445686cba3
using dict and pool in opt_reduce
2014-12-28 21:27:05 +01:00
Clifford Wolf
951c72ba52
bugfix in opt_share
2014-12-28 21:26:36 +01:00
Clifford Wolf
3da46d3437
Renamed hashmap.h to hashlib.h, some related improvements
2014-12-28 17:51:16 +01:00
Clifford Wolf
6c8b0a5fd1
More dict/pool related changes
2014-12-27 12:02:57 +01:00
Clifford Wolf
66ab88d7b0
More hashtable finetuning
2014-12-27 03:04:50 +01:00
Clifford Wolf
ec4751e55c
Replaced std::unordered_set (nodict) with Yosys::pool
2014-12-26 21:59:41 +01:00
Clifford Wolf
9e6fb0b02c
Replaced std::unordered_map as implementation for Yosys::dict
2014-12-26 21:35:22 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
b748622a7f
Added "test_cell -muxdiv"
2014-12-25 19:22:39 +01:00
Clifford Wolf
7dece74fae
Added "test_cell -w" feature
2014-12-25 17:04:13 +01:00
Clifford Wolf
170788a3de
Fixed simplemap for $ne cells with output width > 1
2014-12-25 16:41:20 +01:00
Clifford Wolf
b6a7e21d2e
Fixed off-by-one bug in "hierarchy -check" for positional module args
2014-12-24 16:26:18 +01:00
Clifford Wolf
aad195b88c
Added "dfflibmap -prepare" help
2014-12-24 12:56:05 +01:00
Clifford Wolf
35f5aa300f
Added "dfflibmap -prepare"
2014-12-24 12:19:20 +01:00
Clifford Wolf
032ce573a3
Added "dff2dffe -direct" for direct gate mapping
2014-12-24 11:39:15 +01:00
Clifford Wolf
8c1a72c2a4
Added "dff2dffe -unmap"
2014-12-24 11:09:01 +01:00
Clifford Wolf
afcacd6437
Added support for gate-level cells in dff2dffe
2014-12-24 10:49:54 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
48ca1ff9ef
Improved ABC clock domain partitioning
2014-12-23 14:08:38 +01:00
Clifford Wolf
5fe02b7965
Indenting fix in show.cc
2014-12-23 13:49:54 +01:00
Clifford Wolf
4f5b97954e
Added "show -colorattr"
2014-12-23 12:29:29 +01:00
Clifford Wolf
a216df0433
Added "abc -markgroups"
2014-12-23 12:29:02 +01:00
Clifford Wolf
76fa527492
Added support for multiple clock domains to "abc" pass
2014-12-21 16:52:05 +01:00
Clifford Wolf
25844b5683
Fixed "abc" pass for clk and enable signals driven by logic
2014-12-21 11:13:25 +01:00
Clifford Wolf
f7b323196f
Added DFFE support to "abc" pass
2014-12-20 00:44:03 +01:00
Clifford Wolf
bacd3699b3
Checking existence of ports in "hierarchy -check"
2014-12-19 18:47:19 +01:00
Clifford Wolf
032511fac8
Added functionality to dff2dffe pass
2014-12-08 15:38:58 +01:00
Clifford Wolf
97487fee32
Added skeleton dff2dffe pass
2014-12-08 14:10:52 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
51cfcd8331
Fixed bug in "hierarchy -top" with array of instances
2014-11-27 12:47:33 +01:00
Clifford Wolf
a112b10934
Introducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
2014-11-09 10:55:04 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
d92fb5b35e
Added missing fixup_ports() calls to "rename" command
2014-11-08 12:38:48 +01:00
Clifford Wolf
420bc05627
Added "Nx" syntax to "show" command for repeating SigChunks
2014-11-08 10:58:57 +01:00
Clifford Wolf
546e8b5fe7
Improved TopoSort determinism
2014-11-07 15:21:03 +01:00
Clifford Wolf
99cdfb3110
Fixed typo in "log_cmd_error_exception"
2014-11-07 12:48:15 +01:00
Clifford Wolf
a346c0bf2b
Made "cover" a compile-time option (disabled by default)
2014-11-06 09:39:55 +01:00
Clifford Wolf
ab28491f27
Added "opt -full" alias for all more aggressive optimizations
2014-10-31 03:36:51 +01:00
Clifford Wolf
c5eb5e56b8
Re-introduced Yosys::readsome() helper function
...
(f.read() + f.gcount() made problems with lines > 16kB)
2014-10-23 10:58:36 +02:00
Clifford Wolf
bb631c6f5c
Also look for yosys-abc in parent dir on win32
2014-10-18 19:01:44 +02:00
Clifford Wolf
41db98ba31
Fixed typo in test_cell
2014-10-18 16:52:06 +01:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
Clifford Wolf
468ae92374
Various win32 / vs build fixes
2014-10-17 14:01:47 +02:00
Clifford Wolf
973d376733
Added genfiles.zip to MXE "make dist"
2014-10-17 12:11:15 +02:00
Clifford Wolf
4df902637a
Various MXE build fixes
2014-10-17 12:04:40 +02:00
William Speirs
31267a1ae8
Header changes so it will compile on VS
2014-10-17 11:41:36 +02:00
Clifford Wolf
18cb8b4636
Don't be too smart with $dff cells with "init" attribute on out signal
2014-10-16 11:49:31 +02:00
Clifford Wolf
66eb254fc2
Some cleanups in opt_clean
2014-10-16 11:46:57 +02:00
Clifford Wolf
c3e9922b5d
Replaced readsome() with read() and gcount()
2014-10-15 01:12:53 +02:00
William Speirs
e5b8390f44
Changed from "and" to "&&"
2014-10-15 00:59:22 +02:00
William Speirs
6433203b39
Wrapped init in std::set constructor
2014-10-15 00:58:05 +02:00
Clifford Wolf
c21c9dab1e
Removed CHECK() macro from libparse.cc (was using non-std c features)
2014-10-13 17:22:06 +02:00
Clifford Wolf
0913e968f5
More win32/abc fixes
2014-10-12 14:48:19 +02:00
Clifford Wolf
0b9282a779
Added make_temp_{file,dir}() and remove_directory() APIs
2014-10-12 12:11:57 +02:00
Clifford Wolf
9b4d171e37
Using stringf() instead of asprintf() in "abc" pass
2014-10-12 11:17:53 +02:00
Clifford Wolf
b1596bc0e7
Added run_command() api to replace system() and popen()
2014-10-12 10:57:15 +02:00
Clifford Wolf
d2b8b48bf3
Renamed "log.cc" to "logcmd.cc" so there aren't two "log.cc" in the source tree
2014-10-11 12:13:46 +02:00
Clifford Wolf
35fbc0b35f
Do not the 'z' modifier in format string (another win32 fix)
2014-10-11 11:42:08 +02:00
Clifford Wolf
8263f6a74a
Fixed win32 troubles with f.readsome()
2014-10-11 11:36:22 +02:00
Clifford Wolf
51b1824979
Disabled "cover -d" on win32
2014-10-11 10:49:43 +02:00
Clifford Wolf
54bf3a95dd
More Win32 build fixes
2014-10-10 18:34:19 +02:00
Clifford Wolf
ee5165c6e4
Moved patmatch() to yosys.cc
2014-10-10 18:20:17 +02:00
Clifford Wolf
774933a0d8
Replaced fnmatch() with patmatch()
2014-10-10 18:02:17 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
7cb0d3aa1a
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
fea11f0fa4
Added API for generic cell cost calculations
2014-10-09 13:59:26 +02:00
Clifford Wolf
ccf7b2e342
Added mxe-based cross build for win32
2014-10-09 10:50:44 +02:00
Clifford Wolf
696d7ed40e
Fixes in "hilomap" help message
2014-10-08 21:38:37 +02:00
Clifford Wolf
9dea161321
sort cell types in "stat" output by name
2014-10-03 19:21:04 +02:00
Clifford Wolf
c5c7066ea6
sat encoding for exclusive $pmux ctrl inputs in "share" pass
2014-10-03 19:01:24 +02:00
Clifford Wolf
3e4b0cac8d
added resource sharing of $macc cells
2014-10-03 12:58:40 +02:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
600c6cb013
remove buffers in opt_clean
2014-10-03 10:04:15 +02:00
Clifford Wolf
7019bc00e4
resource sharing of $alu cells
2014-10-03 09:55:50 +02:00
Clifford Wolf
2ee03f5da4
set "keep" on modules with $assert cells in "hierarchy"
2014-09-30 19:16:40 +02:00
Clifford Wolf
0b8cfbc6fd
Added support for "keep" on modules
2014-09-29 12:51:54 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
13117bb346
Re-enabled assert for new logic loops in "share" pass
2014-09-21 19:44:08 +02:00
Clifford Wolf
96e821dc6c
Various improvements regarding logic loops in "share" results
2014-09-21 19:36:56 +02:00
Clifford Wolf
d6e2ace95b
Logic loop bugfix for "share" pass
2014-09-21 15:13:44 +02:00
Clifford Wolf
b28be0759f
Added "share -limit"
2014-09-21 15:13:06 +02:00
Clifford Wolf
a6c08b40fe
Still loop bug in "share": changed assert to warning
2014-09-21 14:51:07 +02:00
Clifford Wolf
8d60754aef
Do not introduce new logic loops in "share"
2014-09-21 13:52:39 +02:00
Clifford Wolf
edf11c635a
Assert on new logic loops in "share" pass
2014-09-21 12:57:33 +02:00
Clifford Wolf
a7758ef953
Added "test_abcloop" command
2014-09-19 15:51:34 +02:00
Clifford Wolf
5827826098
Small improvements in "abc" command handle_loops() function
2014-09-19 14:05:41 +02:00
Clifford Wolf
3aa003c8e9
Using "NOT" instead of "INV" as cell name in default abc genlib file
2014-09-19 13:15:31 +02:00
Clifford Wolf
f7bb8f244b
Alphabetically sort port names in "show" output
2014-09-19 11:13:10 +02:00
Clifford Wolf
f56b92818b
Do not run "scorr" in "abc -fast"
2014-09-18 19:00:21 +02:00
Clifford Wolf
815fab9d71
Added "abc -fast"
2014-09-18 12:57:37 +02:00
Clifford Wolf
9ae559b990
Fixed $_NOR vs. $_NOR_ typo in abc.cc
2014-09-16 12:45:05 +02:00
Clifford Wolf
ae02d9cb9a
Fixed $memwr/$memrd order in memory_dff
2014-09-16 12:40:58 +02:00
Clifford Wolf
b86410b2ab
More aggressive $macc merging in alumacc
2014-09-15 12:42:11 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
fcbda07411
Improved maccmap tree bit packing
2014-09-15 12:00:19 +02:00
Clifford Wolf
2cbdbaad1f
Fixed wreduce $shiftx handling
2014-09-15 11:29:09 +02:00
Clifford Wolf
7e156a5419
Fixed techmap_wrap for techmap_celltype
2014-09-14 15:34:36 +02:00
Clifford Wolf
014bb34e0e
Various fixes/cleanups in alumacc and maccmap
2014-09-14 14:49:53 +02:00
Clifford Wolf
124e759280
Added techmap_wrap attribute
2014-09-14 14:49:26 +02:00
Clifford Wolf
b34ca15185
alumacc fix for $pos cells
2014-09-14 14:00:14 +02:00
Clifford Wolf
0df1d9ad72
Extract $alu cells in alumacc
2014-09-14 13:23:44 +02:00
Clifford Wolf
7b16c63101
Merge $macc cells in alumacc pass
2014-09-14 11:21:37 +02:00
Clifford Wolf
0b72f0acb1
Basic $macc extract in alumacc
2014-09-14 10:45:28 +02:00
Clifford Wolf
ff157fb74f
alumacc skeleton
2014-09-14 10:02:00 +02:00
Clifford Wolf
aab0e3bf70
Cleanup in wreduce
2014-09-14 10:01:30 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
1a88e47396
Trim msb/lsb zero bits from full adder in maccmap
2014-09-08 11:21:58 +02:00
Clifford Wolf
6747a7047e
Added "test_cell -const"
2014-09-08 11:12:39 +02:00
Clifford Wolf
c50b841b29
Added 'techmap_maccmap' techmap attribute
2014-09-07 18:23:37 +02:00
Clifford Wolf
015dcdc84c
Added "maccmap" command
2014-09-07 18:23:04 +02:00
Clifford Wolf
15b3c54fea
Added "test_cell -nosat"
2014-09-07 17:05:41 +02:00
Clifford Wolf
9329a76818
Various bug fixes (related to $macc model testing)
2014-09-06 20:30:46 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
b847ec8a0b
Added $macc cell type
2014-09-06 15:47:46 +02:00
Clifford Wolf
34af6a1303
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 11:46:44 +02:00
Clifford Wolf
e1743b3bac
Added "test_cell -script"
2014-09-06 11:46:07 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
f5a40e7043
Fixed "opt_const -fine" for $pos cells
2014-09-04 08:55:58 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
5733f4a39d
Fixed "test_cells -vlog"
2014-09-03 13:43:37 +02:00
Clifford Wolf
f1869667ca
Improvements in "test_cell -vlog"
2014-09-02 23:21:15 +02:00
Clifford Wolf
66bf2bb92e
Added test_cell -vlog
2014-09-02 22:49:43 +02:00
Clifford Wolf
acd7a99aef
Added SAT testing to test_cell eval stage
2014-09-02 17:28:13 +02:00
Clifford Wolf
37fe7c7bdf
Removed references to yosys-svgviewer from docs
2014-09-02 04:03:06 +02:00
Clifford Wolf
9f00a0cd2d
Using "xdot" instead of "yosys-svgviewer" in show command
2014-09-02 03:28:46 +02:00
Clifford Wolf
630befdf6d
Added $alu support to test_cell
2014-09-01 16:36:04 +02:00
Clifford Wolf
c7f81e4e49
Added "test_cell -simlib -v"
2014-09-01 15:37:21 +02:00
Clifford Wolf
826fdb34d8
Added "techmap -autoproc"
2014-09-01 15:36:29 +02:00
Clifford Wolf
27a1bfbec6
Fixes in old SAT example.ys
2014-09-01 11:45:47 +02:00
Clifford Wolf
d5148f2e01
Moved "share" and "wreduce" to passes/opt/
2014-09-01 11:45:26 +02:00
Clifford Wolf
e07698818d
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
Clifford Wolf
e3664066d5
Added eval testing to test_cell
2014-08-31 18:08:42 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
2a1b08aeb3
Added design->scratchpad
2014-08-30 19:37:12 +02:00
Clifford Wolf
6ff46323a3
Improved write address decoder generation memory_map
2014-08-30 18:18:15 +02:00
Clifford Wolf
66763fad4e
Using worker class in memory_map
2014-08-30 17:39:08 +02:00
Clifford Wolf
3a7d5d188d
Don't change existing binary FSM encoding if it is already optimal
2014-08-30 14:43:06 +02:00
Clifford Wolf
f910481f35
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
2014-08-30 14:34:49 +02:00
Clifford Wolf
ab019b0bd5
Improved handling of $pmux cells in fsm_extract
2014-08-30 14:11:57 +02:00
Clifford Wolf
d148b0af0d
Fixed inserting of Q-inverters in dfflibmap
2014-08-27 19:44:12 +02:00
Clifford Wolf
084685f480
Implemented "rename -enumerate -pattern"
2014-08-26 12:51:08 +02:00
Clifford Wolf
7bbbe3580d
Optimize shift ops with constant rhs in opt_const
2014-08-24 17:08:43 +02:00
Clifford Wolf
641501203c
Added some additional log messages to opt_const
2014-08-24 17:08:43 +02:00
Clifford Wolf
9c5a63c52c
azonenberg: Make dump_vcd save model when temporal induction fails due to step limit
2014-08-24 13:27:40 +02:00
Clifford Wolf
c642dd0b3e
Only call proc_share_dirname() in techmap when necessary
2014-08-23 15:32:00 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
fff12c719f
Added "stat -width"
2014-08-22 17:20:28 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
a3494fa9ed
Added "plugin" command
2014-08-22 14:00:11 +02:00
Clifford Wolf
410d043dd8
Renamed toposort.h to utils.h
2014-08-17 00:55:35 +02:00
Clifford Wolf
7f734ecc09
Added module->uniquify()
2014-08-16 23:50:36 +02:00
Clifford Wolf
3b9157f9a6
Added "test_cell -s <seed>"
2014-08-16 19:44:31 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
eb17fbade5
Added "opt -fast"
2014-08-16 15:34:15 +02:00
Clifford Wolf
674f421b47
Bugfix in iopadmap
2014-08-15 14:29:42 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
ca87116449
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
Clifford Wolf
d320e75087
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
28cf48e31f
Some improvements in FSM mapping and recoding
2014-08-14 11:22:45 +02:00
Clifford Wolf
996c06f64d
Added "abc -D" for setting delay target
2014-08-14 11:05:25 +02:00
Clifford Wolf
28bc7aeb93
Filter ANSI escape sequences from ABC output
2014-08-13 13:40:29 +02:00
Clifford Wolf
9d353fc543
Fixed handling of constant-true branches in proc_clean
2014-08-12 17:35:22 +02:00
Clifford Wolf
788bd02f97
Fixed FSM mapping for multiple reset-like signals
2014-08-10 12:04:02 +02:00
Clifford Wolf
9d4362990f
Fixed "share" for complex scenarios with never-active cells
2014-08-09 17:07:20 +02:00