cb07848475
[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
2021-03-20 18:11:54 -06:00
f3792bc6f6
[Test] Update VTR benchmark test case to include DSP example benchmark
2021-03-20 18:09:19 -06:00
477a522885
[HDL] Rename tech lib to be consistent with arch name changes
2021-03-20 18:08:03 -06:00
911979a731
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
2021-03-20 18:04:59 -06:00
1185f7b8bf
[Script] Add a template yosys script to enable DSP mapping
2021-03-20 17:05:30 -06:00
6bf4880c50
[benchmark] Add vtr benchmark
2021-03-17 15:24:26 -06:00
f9dc7c1b54
[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
2021-03-17 15:15:22 -06:00
08a86e056a
[Test] Add vtr benchmark regression test
2021-03-17 15:13:58 -06:00
7eeb35d21f
[Script] Bug fix in yosys script to synthesis BRAM
2021-03-17 15:12:04 -06:00
1976a8068f
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
2021-03-17 15:11:17 -06:00
deee7ba366
[Script] Add example script to run vtr benchmarks
2021-03-17 15:10:56 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
76113a80fa
[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
2021-03-17 15:09:12 -06:00
e1f8b252b1
Merge branch 'master' into yosys_heterogeneous_block_support
2021-03-16 20:05:21 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
094b3e9b90
[Script] Use parameters in template yosys script supporting BRAMs
2021-03-16 19:51:48 -06:00
cea43c2c45
[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
2021-03-16 18:04:31 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
84778bd38d
[Script] Add new yosys script to support architectures with BRAMs
2021-03-16 16:52:18 -06:00
090f483a11
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
2021-03-16 16:45:57 -06:00
76837e02e6
[Script] Rename yosys script supporting bram and restructure techlib files
2021-03-16 16:16:53 -06:00
e61857aa2b
Merge branch 'master' into ganesh_dev
2021-03-11 19:17:02 -07:00
366bec232c
[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
2021-03-11 15:25:48 -07:00
bb2a02c9ad
[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[ https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v ]
2021-03-11 15:23:14 -07:00
baf162e401
[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
2021-03-10 22:45:19 -07:00
a6186db315
[Test] Update bitstream annotation with new syntax
2021-03-10 20:45:17 -07:00
7d07f5d8cb
[Test] Update bitstream setting example with mode bit overwriting
2021-03-10 15:34:53 -07:00
b42541d84e
[Flow] Support multiple iterations in rewriting yosys scripts
2021-03-10 14:10:35 -07:00
90a00da1df
[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
2021-03-10 13:56:35 -07:00
d21909ad6c
[Test] Use custom rewriting script in lut_adder test
2021-03-10 13:48:20 -07:00
0e772bc3b4
[Script] Patch the yosys rewrite script to avoid existing blif outputs
2021-03-10 13:47:30 -07:00
7adb78b159
[Script] Add a template yosys script with rewriting at the end
2021-03-10 13:40:31 -07:00
035043d0d8
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
2021-03-10 13:36:11 -07:00
5d46537b5b
[Script] Allow users to specify custom post-synthesis verilog for simulation
2021-03-10 11:45:55 -07:00
aafd87c3f9
[Flow] Update flow-run to support custom yosys rewrite scripts
2021-03-10 11:36:29 -07:00
db8ea86b2f
update tests to use no_ff_map and remove tests that need async set/reset for now
2021-03-10 10:04:45 -08:00
608bd1f658
comment out desings that utilize local async reset/preset
2021-03-09 19:24:01 -08:00
7f4c20ff33
comment out desings that utilize local async reset/preset
2021-03-09 10:37:06 -08:00
c4b83aeaa9
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
2021-03-09 00:46:40 -08:00
2daa770319
[Arch] Update openfpga architecture to include quicklogic cell sim
2021-03-08 21:40:29 -07:00
812d8c950e
[Script] Update quicklogic's script to output correct verilog file name
2021-03-08 21:39:44 -07:00
37aa42d305
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
2021-03-08 21:38:51 -07:00
c53c41b7a5
[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
2021-03-08 21:09:23 -07:00
131643dcc0
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
2021-03-08 21:08:55 -07:00
b860722893
Fixed parameter ys_rewrite_params name bug
2021-03-08 10:34:39 -07:00
52de55e7eb
Merge branch 'master' into ganesh_dev
2021-03-08 10:15:06 -07:00
906d2fa72d
Merge branch 'master' into shift_reg
2021-03-08 09:24:29 -07:00
7a35811430
[Flow] Yosys rewrite support
2021-03-08 00:35:47 -07:00
67cd9a69b7
[Flow] Extended yosys variable subtitution
2021-03-08 00:21:07 -07:00
7945628307
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
2021-03-07 22:25:01 -08:00
6a1ce01084
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
2021-03-07 22:02:11 -08:00
ce76c58422
add shift register test case
2021-03-05 09:06:05 -08:00
2b2acae757
Adding command to generate verilog file out of yosys run
2021-03-05 04:07:02 -08:00
0cbad747a1
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
2021-03-04 01:10:47 -08:00
817729ac86
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
2021-03-01 22:31:15 -08:00
e34380a654
Merge branch 'master' into default_net_type
2021-03-01 08:38:58 -07:00
ea4aee8cb2
For time-being yosys script running in no_adder mode.
2021-02-28 22:07:23 -08:00
0038496d9c
Replacing -openfpga with -family qlf_k4n8
2021-02-28 21:08:47 -08:00
b4b6ada06f
[Script] Correct bugs in example scripts using default_net_type
2021-02-28 16:31:44 -07:00
86930d63d3
[Test] Deploy new test to CI
2021-02-28 16:18:46 -07:00
b90a17543d
[Test] Add new test case to test default nettype in different verilog syntax
2021-02-28 16:16:45 -07:00
9f4d05da67
[Test] Bug fix for new test case
2021-02-28 16:11:30 -07:00
8cc2c7d924
[Script] Bug fix for default net type example script
2021-02-28 12:35:44 -07:00
6d419fed41
[Test] Deploy verilog default net wire type test case to CI
2021-02-28 12:33:48 -07:00
18a7041424
[Test] Add default net type test for explicit port mapping
2021-02-28 12:31:32 -07:00
0723b79bce
[Script] Add example script for verilog default net type
2021-02-28 12:29:56 -07:00
27200e3daa
[Test] Update regression test cases for fpga verilog
2021-02-28 12:24:36 -07:00
ff29cc3dff
[Test] Move tests to a test group
2021-02-28 12:23:35 -07:00
9cb1ca42fe
[Test] Deploy default net type option to test case
2021-02-28 12:20:43 -07:00
ae05871b1f
[Script] Remove default net type from an example script; Limit it to some test cases
2021-02-28 12:19:14 -07:00
d7eb159726
[Script] Add default net type option to example openfpga shell scripts
2021-02-28 12:08:30 -07:00
0d82e4939c
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
2021-02-26 09:35:40 -07:00
744d87cb4e
[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
2021-02-26 09:34:52 -07:00
870d3a0e27
Merge branch 'master' into dev
2021-02-26 09:28:42 -07:00
1082d3c677
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
2021-02-25 23:39:07 -08:00
1e48d4f6dc
Modifying custom yosys script file name
2021-02-25 22:21:39 -08:00
4c2a88e27f
[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
2021-02-24 11:51:10 -07:00
0ce9b66c75
[Arch] Add a dummy adder lut circuit model to support HDL simulation
2021-02-24 10:09:44 -07:00
86a602d381
[Test] Deploy new test to CI
2021-02-23 19:55:07 -07:00
a62786986b
[Test] Turn off verification in adder lut test temporarily
2021-02-23 19:03:25 -07:00
ad25944e59
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
2021-02-23 19:00:27 -07:00
53df7f69e7
[Test] Bug fix in the test case using lut adder
2021-02-23 16:59:46 -07:00
db71cc8a16
[Test] Add LUT adder test using quicklogic synthesis script
2021-02-23 16:50:58 -07:00
19f6b221b1
[Test] Rework comments on runtime
2021-02-22 15:25:57 -07:00
4803b0ce42
[Test] Add test case for sdc controller
2021-02-22 15:02:14 -07:00
c7a9a4e896
[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
2021-02-22 15:01:50 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
2e2b1cb6e7
[Test] Use hetergenenous FPGA architecture in quicklogic tests
2021-02-22 13:41:04 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
b3fed683f9
[Test] Deploy test to CI
2021-02-22 12:43:30 -07:00
bc30f62c5a
[Test] Add test for sdc controller
2021-02-22 12:41:53 -07:00
60dc194d8f
[Test] Bug fix in the 5clock test case
2021-02-22 11:46:23 -07:00
71e0026a50
[Test] Add new test for 5-clock counter to quicklogic tests
2021-02-22 11:32:17 -07:00
2bb588dacf
[Flow] Add a new script for generating bitstream for multi-clock architectures
2021-02-22 11:31:24 -07:00
77896379e2
[Arch] Add simulation setting for 8-clock architectures
2021-02-22 11:10:03 -07:00
16debe49f6
[Arch] Add more comments on the 4 clock simulation setting file
2021-02-22 11:04:34 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
b9c2564a7e
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
2021-02-22 10:49:21 -07:00
bc8aa0ebc6
[Test] Remove routing test from quicklogic's flow test
2021-02-22 10:22:47 -07:00
2dbdc2644f
[Benchmark] Remove replicate micro benchmarks
2021-02-22 10:22:19 -07:00
9b6b2068ee
[Test] Move MCNC test to benchmark sweep test group
2021-02-22 10:18:34 -07:00
c1f4a434e4
[Doc] Update README for the regression test tasks
2021-02-22 10:17:02 -07:00
d6a02a985e
Merge pull request #248 from lnis-uofu/add_quicklogic_tests
...
Disabling verilog testbench generation for quicklogic tests
2021-02-22 09:02:29 -07:00
d842026672
Disabling verilog testbench generation for quicklogic tests
2021-02-21 21:58:23 -08:00
be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
...
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
576e6753f6
Removing 2 more tests which are variant of and design
2021-02-19 09:11:19 -08:00
d4c5a5655a
Removing blif file as well as and2 testcase
2021-02-19 08:55:17 -08:00
6de0954ca5
Uncommenting all benchmarks except 2 that requires multiple clocks
2021-02-19 08:40:26 -08:00
e08ac1a41e
[Test] Deploy synthesizable verilog test to CI
2021-02-18 19:37:45 -07:00
e19fc15fec
[Test] bug fix in test case
2021-02-18 19:37:45 -07:00
affc8cbbc4
[Test] Deploy test to CI
2021-02-18 19:37:45 -07:00
2e88b035ed
[Test] Add wire LUT repacker test case
2021-02-18 19:37:44 -07:00
1f097abe99
[Benchmark] Add micro benchmark for FIR filter
2021-02-18 19:37:44 -07:00
69cdc11ea5
Uncommenting the tests that are running fine
2021-02-18 04:17:12 -08:00
d85d6e964e
Merge pull request #227 from watcag/master
...
Standard-cell flow
2021-02-17 10:11:34 -07:00
7ee01711c2
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
2021-02-17 00:06:59 -08:00
44a979288b
Adding quicklogic tests and updating the corresponding conf file to run them
2021-02-16 23:08:38 -08:00
a819375f69
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
2021-02-16 16:53:13 -07:00
2c2e493739
[Test] Remove quicklogic test from basic tests
2021-02-16 12:29:10 -07:00
9c19e2b365
[Test] Move regression test scripts from workflow to openfpga_flow
2021-02-16 11:55:47 -07:00
426b6449d8
change the test to turn off power analysis
2021-02-15 02:45:38 -08:00
3a587f663a
copy yosys output file in case power analysis setting is off
2021-02-15 02:36:02 -08:00
e683e00032
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
2021-02-10 14:50:11 -07:00
9b86f3bb85
Merge branch 'master' into dev
2021-02-09 22:40:45 -07:00
22e675148e
[HDL] Add HDL codes for a super LUT with embedded carry logic
2021-02-09 21:13:22 -07:00
b81b74aa7c
[Arch] Patch architecture to support superLUT-related XML syntax
2021-02-09 20:23:32 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
3ae501a5ea
[Test] Update test case to use dedicated eblif file
2021-02-09 15:51:57 -07:00
1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
4c7f4bd82f
ahoy nice
2021-02-09 17:38:19 -05:00
2b51b36dd6
[Test] Now use the super LUT arch in the test case
2021-02-09 15:27:44 -07:00
56284059de
[Test] Add a test case for a super LUT
2021-02-09 15:25:32 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
71c76df063
default to ns for time unit -- synopsys dc whines
2021-02-09 17:08:38 -05:00
6bb2e29f17
default to ns for time unit -- synopsys dc whines
2021-02-09 17:04:52 -05:00
87c69460df
what is going on
2021-02-09 11:33:08 -05:00
cc74c6268a
trying fix chan width
2021-02-09 11:28:19 -05:00
95fe4d7dae
adding dff synth
2021-02-09 10:34:54 -05:00
b14b5f975d
adding sweep for W
2021-02-09 08:48:25 -05:00
d7967da328
bugfix in alt
2021-02-08 23:04:00 -05:00
485708423c
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
cf154d8bb9
no need for dff*, but need tap_buf4
2021-02-08 22:29:55 -05:00
e14c0bf0c4
no need for dff*, but need tap_buf4
2021-02-08 22:28:42 -05:00
45437fbc46
no need for dff*, but need tap_buf4
2021-02-08 22:27:57 -05:00
853bf8af43
typos fixed;
2021-02-08 22:03:14 -05:00
d040ba569c
merge for consideration;
2021-02-08 21:29:34 -05:00
94f858fcde
merge for consideration;
2021-02-08 21:27:01 -05:00
0c6d27cf7e
merge for consideration;
2021-02-08 21:26:48 -05:00
b4185f7e8c
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
2021-02-08 21:11:30 -05:00
2344cdcabc
merge
2021-02-08 21:11:28 -05:00
1ce94040da
Merge pull request #221 from lnis-uofu/flow_dev
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[Flow] Support multi-user environment for running task
2021-02-08 12:43:57 -07:00
80a4872ba0
Merge pull request #222 from lnis-uofu/gg_cleanup
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[Flow] ACE is optional during flow script, only runs when power estimation is on
2021-02-08 10:08:47 -07:00
ede5f8ed58
[Flow] Support multi-user enviroment for running task
2021-02-07 22:11:04 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
ee14c15e58
Merge pull request #212 from lnis-uofu/soft_adder_lut_support
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Support overloading LUT bitstream from attributes in .eblif file format
2021-02-04 21:55:02 -07:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
224bf6c686
Merge branch 'master' into dev
2021-02-04 17:21:15 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
6cdc31f073
[Flow] ACE is optional duign flow script
2021-02-03 19:07:48 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
df4a397470
[Cleanup] Removed deadcode
2021-02-03 10:35:14 -07:00
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
31441c0b64
[Test] Deploy adder_8 to soft adder test
2021-02-03 09:26:38 -07:00
05d63567d0
[Benchmark] Use latest adder eblif file
2021-02-03 09:21:38 -07:00
ebe66dea35
Bumping up latest yosys changes related to adder tech mapping
2021-02-03 14:30:06 +05:30
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
8e36ed1ab6
[Test] Update task configuration to use and2 eblif
2021-02-02 15:01:15 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
5e2847bc41
[Test] Update test case to use eblif file
2021-02-02 09:33:41 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
d3397f6936
[Script] Remove activity from bitstream setting example script
2021-02-02 09:25:36 -07:00
9ff5e7926b
[Test] Update test case to use the adder benchmark
2021-02-02 09:24:39 -07:00
7f14dfbe87
[Script] Add example script to use bitstream setting
2021-02-02 09:18:08 -07:00
04594cb7ab
[Test] Adapt bitstream annotatin file to parser's requirement
2021-02-01 17:38:36 -07:00
280c9620aa
[Test] Add an example bitstream annotation file
2021-02-01 16:01:21 -07:00
a6354fab7c
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
df88e2adc0
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
2021-02-01 14:26:11 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
b215b868c1
[HDL] Bug fix in HDL netlist due to port name mismatching
2021-02-01 11:35:25 -07:00
e4abe263c3
[Arch] Bug fix
2021-02-01 11:29:27 -07:00
fb05e1a938
[Arch] bug fix due to using openfpga cell library
2021-02-01 11:27:21 -07:00
940dce469a
[Test] Bug fix for test case configuration
2021-02-01 11:19:47 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
af630dab1e
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
2021-02-01 10:53:38 -07:00
9cce411eda
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
0eb949b85a
[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
2021-02-01 10:34:32 -07:00
e0e2506e32
[HDL] Remove redundant comments
2021-02-01 10:33:08 -07:00
39543f7945
[HDL] Add carry mux2 to cell library
2021-02-01 10:23:46 -07:00
6ede799c16
[Arch] Add openfpga architecture for the QLSOFA
2021-02-01 10:15:35 -07:00
df05911d24
Merge branch 'master' into soft_adder_lut_support
2021-02-01 10:02:05 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
a70725b4be
Merge branch 'master' into dev
2021-01-29 11:41:40 -07:00
8b74947737
[Script] Now multi-clock openfpga shell script no longer needs activity file
2021-01-29 11:40:33 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
0b82b6439b
[Regression] Upgraded runtime enviroment to python3.8
2021-01-26 16:40:45 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
3fdd5ae8b3
[Script] Use pin constraints in template script
2021-01-19 17:42:25 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
12e0efd03e
[Script] Add an example openfpga script to use repack design constraints
2021-01-17 10:33:56 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
89f9d24d32
[Flow] Update simulation settings for multiple clock to allow unique clock port name
2021-01-15 10:35:43 -07:00
dbed04b53b
[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
2021-01-14 15:42:21 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
923f3a3401
[Flow] Add an example simulation settings for a 4-clock FPGA fabric
2021-01-13 17:29:39 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
c5a2027f36
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
2021-01-13 15:41:48 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
ccf3e037ff
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
2021-01-13 13:31:06 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
2f1aceda67
[Doc] Update documentation about architecture naming rules
2021-01-12 18:01:24 -07:00
9fa49c401c
[Arch] Add openfpga architecture which uses 4 global clocks
2021-01-12 18:00:22 -07:00
16b4e89326
[Doc] Update documentation for VPR architectures
2021-01-12 17:57:40 -07:00
7ccdff4543
[Arch] Add an architecture using 4 clocks
2021-01-12 17:55:57 -07:00
3790f2c26a
[Benchmark] Add 2-clock micro benchmark
2021-01-12 17:48:52 -07:00
a0b9f2b40d
Merge pull request #170 from lnis-uofu/dev
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Extended Support on Defining Global Ports from Physical Tile Ports
2021-01-11 10:02:31 -07:00
e58e1e86c2
[Test] Update test case to use new shell script
2021-01-10 11:09:10 -07:00
18d2a8ce19
[Flow] Add new script for fixed device layout using global tile clock
2021-01-10 11:08:02 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
1c68e43acf
[Test] Add new test case for registerable I/O architecture
2021-01-10 11:00:21 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
dfb3e32147
[Arch] Add openfpga archiecture for registerable I/O
2021-01-10 10:54:41 -07:00
853e7b1a40
[Arch] Add vpr architecture where I/O can be either combinational or registered
2021-01-10 10:54:09 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
6521aa2e7a
[Benchmark] Bug fix in pipelined and2 benchmark
2021-01-10 10:27:59 -07:00
4412bbd084
[Benchmark] Add a micro benchmark to test pipelined architecture
2021-01-10 10:21:30 -07:00
0b74575606
[Arch] Update arch using global reset tile port
2021-01-09 18:04:55 -07:00
7b24da267a
[Arch] Remove port size XML syntax
2021-01-09 16:30:46 -07:00
9f12b25a24
[Arch] Add port size to global port defined thru tile annotation
2021-01-09 16:23:28 -07:00
0f5f0a3527
[Arch] Add x,y coordinates to global port definition
2021-01-09 15:50:09 -07:00
a14a56772a
[Arch] Introduce new XML syntax for global port in tile annotation
2021-01-09 15:48:42 -07:00
8a5741b1ae
Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
2021-01-08 07:08:24 -08:00
a813c9016b
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
2021-01-04 17:39:13 -07:00
06af30ef10
[Test] Add test case for the SCFF usage in configuration chain
2021-01-04 17:30:19 -07:00
709ee1b842
[HDL] Update dff netlist for SCFF used in configuration chain
2021-01-04 17:17:35 -07:00
c97a92d628
[Arch] Patch openfpga architecture for ccff circuit model port requirement
2021-01-04 17:15:50 -07:00
294ad97d38
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
2021-01-04 14:56:49 -07:00
722a9bcf63
[HDL] Add scan-chain DFF cell with configuration enable signal
2021-01-04 14:31:26 -07:00
2484721a45
Updating write_verilog_testbench by removing option explicit_port_mapping
2020-12-22 22:17:50 -08:00
3c9e4919b4
Updating variable name in ys to call BLIF output file.
2020-12-18 03:18:46 -08:00
1f994319fd
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
2020-12-16 04:19:56 -08:00
891e2f8aa3
Adding arch xml from SOFA repo. Also updating the script with its file location
2020-12-16 04:14:18 -08:00
0ee3efb306
Adding a testcase to run yosys quicklogic flow
2020-12-10 02:41:43 -08:00
6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
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Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
6001da3a40
[Arch] Bug fix in tileable I/O arch example
2020-12-04 17:56:54 -07:00
1d0bdcfeca
[Arch] Simplify the grid layout modeling
2020-12-04 17:38:44 -07:00
1c3f625e41
[Arch] Force empty tiles at corners for tileable I/O arch example
2020-12-04 17:11:06 -07:00
0cb8457e21
[Test] Add test case for tileable I/O
2020-12-04 16:02:47 -07:00
186eb0f0a4
[Arch] Add tileable I/O architecture example
2020-12-04 15:59:39 -07:00
289d9d2169
[Bugfix] Honors yosys_tmpl parameter in flow script
2020-12-03 12:24:24 -07:00
412fb5bb31
[Arch] Bug fix due to valid default value parser
2020-12-02 17:51:50 -07:00
179b0ce304
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
2020-11-30 18:11:47 -07:00
c7604ab94f
[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
2020-11-30 18:02:00 -07:00
ff53d2c375
[HDL] Add new Scan-chain DFF cell
2020-11-30 17:54:10 -07:00
ad703ad85b
[HDL] Add new gpio cell with protection circuitry
2020-11-30 17:52:39 -07:00
27a480b5f8
[Test] arch name fix in the test case
2020-11-30 17:45:54 -07:00
7a0a3398d4
[Arch] Add new architecture to test global reset ports defined thru tile ports
2020-11-30 17:43:41 -07:00
a1d3b439d3
[Test] Add a new test case to define a global reset port from a global tile port
2020-11-30 17:19:12 -07:00
a60bd4d14a
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
7db030018c
[Bug] Fixed variable file location
2020-11-25 22:44:40 -07:00
b8559249dc
[Test] Bug fix in task configuration file
2020-11-25 22:23:27 -07:00
26e4db56ad
[Test] Add new test case for the native fracturable LUT4
2020-11-25 22:21:23 -07:00
17070c6405
[Doc] Update README in openfpga arch directory for native fracturable LUT design
2020-11-25 22:19:20 -07:00
f6a667de58
[Arch] Add openfpga architecture using native fracturable LUT
2020-11-25 22:18:03 -07:00
eda671592e
[Doc] Update README about new keyword about fracturable LUT
2020-11-25 22:12:56 -07:00
0f841aa6d1
[Arch] Add an example architecture using native fracturable LUT
2020-11-25 22:11:14 -07:00
59bd7d0f18
[Flow] Changed substitute to safe_sustitute option
2020-11-25 22:09:36 -07:00
fefba0db59
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
2020-11-25 17:29:53 -07:00
1d993296d8
[Flow] Example of using test variable in task conf
2020-11-25 17:25:12 -07:00
1554f583b7
[Flow] Now support explicit variable file for task
2020-11-25 17:22:41 -07:00
fd80cacaa3
[Flow] Add example script for behaviorial verilog generation
2020-11-22 21:14:10 -07:00
617f7e3062
[Flow] disable signal initialization for behavioral verilog generation
2020-11-22 21:13:22 -07:00
5eb04e6fff
[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
2020-11-22 20:53:32 -07:00
655da9f3d0
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
2020-11-22 16:37:19 -07:00
348872f8a4
[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
2020-11-22 16:12:28 -07:00
845436fa71
[Test] Add sequential benchmark for global tile clock test case
2020-11-17 14:34:54 -07:00
91b0dbbaa2
[Script] Add example openfpga shell run script when using global tile clocks
2020-11-17 14:33:12 -07:00
485258a9ea
[Test] Add test case for global clock from tiles
2020-11-10 19:24:25 -07:00
f29916921a
[Arch] Add openfpga arch for using global clocks from tiles
2020-11-10 19:20:08 -07:00
a6531d9e8d
[Arch] Add k4 arch using global clock from tile port (with zero fc)
2020-11-10 19:17:34 -07:00
75ce4b5e25
[Arch] Fine tune example arch
2020-11-10 14:38:47 -07:00
d127304760
[Arch] Update sample arch using local clock from physical tile ports
2020-11-10 14:31:58 -07:00
4ca2a129c2
[Arch] Add an sample architecture where global clock port is defined from tile ports
2020-11-10 11:47:03 -07:00
70734abc35
[Arch] Remove QN from stdcell arch
2020-11-06 11:20:13 -07:00
1a79a55646
[HDL] Add DFF cell with reset but only 1 output
2020-11-06 11:19:19 -07:00
2aab8bf910
[Arch] Use single-output DFF for a standard cell FPGA
2020-11-06 10:26:39 -07:00
7d46b35296
[HDL] Add single-output DFF HDL
2020-11-06 10:18:37 -07:00
55f7a2c187
Merge pull request #116 from LNIS-Projects/dev
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Extended I/O Support for SoC I/O interface
2020-11-04 21:55:37 -07:00
bce8233019
[Arch] Bug fix in caravel arch
2020-11-04 20:58:58 -07:00
6b48ee7f0b
[Test] Add new test for caravel io support
2020-11-04 20:58:40 -07:00
c85edb4738
[Arch] Bug fix for embedded io arch
2020-11-04 20:52:47 -07:00
a6c7bb2c48
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
dd86f7f464
[Arch] Path architecture for caravel i/o interface
2020-11-04 17:16:21 -07:00
c074e88dcd
[HDL] Add embedded I/O HDL for Caravel SoC interface
2020-11-04 17:09:59 -07:00
aebf7453d0
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
2020-11-04 16:57:00 -07:00
61376a2979
[Test] Add test cases for various tile organization
2020-11-04 16:32:52 -07:00
cf455df555
[Arch] Add architecture for bottom-right and top-left tile organization
2020-11-04 16:24:36 -07:00
46ca406f10
[Arch] Add a new vpr architecture with new tile organization
2020-11-04 16:20:01 -07:00
049ca14461
[Doc] Add new naming rules for vpr architecture files
2020-11-04 16:17:56 -07:00
5d41cc6d23
Merge pull request #114 from LNIS-Projects/dev
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Support I/O interfaces for Embedded FPGAs
2020-11-02 21:10:52 -07:00
c036c87d6d
[HDL] Bug fix in the GP output pad
2020-11-02 18:37:53 -07:00
3b49e6d090
[Arch] Patch embedded IO architecture by forcing only 1 pad per block
2020-11-02 15:39:31 -07:00
c512644a09
[Arch] Patch embedded I/O example architecture
2020-11-02 15:16:19 -07:00
7e9e0ec9d4
[HDL] Bug fix in I/O HDL code
2020-11-02 15:15:45 -07:00
2f237a6240
[HDL] Add HDL codes for embedded I/Os
2020-11-02 14:01:27 -07:00
55b77ac6cb
[Arch] Bug fixed in embedded FPGA architecture
2020-11-02 13:57:15 -07:00
a7e7fa2005
[Arch] Update arch with true embedded I/O definition
2020-11-02 13:29:40 -07:00
65ca53ac98
[Test] Update test case with the new arch name
2020-11-02 13:16:42 -07:00
8c8190047f
[Arch] Rename architecture files for embedded I/Os
2020-11-02 13:15:19 -07:00
bc00dee858
[Test] Add test case for embedded I/O
2020-11-02 12:28:25 -07:00
f86f43d287
[Arch] Add openfpga architecture file for constrained pin equivalence
2020-11-02 12:27:40 -07:00
795b30f76b
[Arch] Add VPR architecture with partial pin equivalence
2020-11-02 11:54:25 -07:00
032cbfb8b2
Merge pull request #113 from LNIS-Projects/dev
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Multi-region support on Frame-based Configuration Protocol
2020-10-31 10:37:38 -06:00
4c14428400
[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
2020-10-30 10:50:00 -06:00
ca7d43275d
[Test] Add test case for multi_region configuration frame
2020-10-30 10:48:29 -06:00
29da368742
[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
2020-10-30 10:46:47 -06:00
b701bd2640
[Arch] Add multi-region architecture example for frame-based protocol
2020-10-30 10:45:14 -06:00
cd0d3dd798
Merge pull request #112 from LNIS-Projects/dev
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Multi-region Memory Bank Configuration Protocol Support
2020-10-29 18:39:44 -06:00
1d930d1b5d
[Architecture] Add missing arch files and bug fix
2020-10-29 18:08:26 -06:00
153b265a6d
[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
2020-10-29 16:32:05 -06:00
241ebf054a
[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
2020-10-29 16:29:46 -06:00
ff386001c4
[Test] Add openfpga task for multi-region memory banks
2020-10-29 13:56:32 -06:00
7534474423
[Arch] Add architecture for multiple-region memory banks
2020-10-29 13:54:51 -06:00
d984547258
Merge pull request #108 from LNIS-Projects/dev
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Add test cases for constant inputs of routing multiplexers
2020-10-14 22:33:14 -06:00
179ae355d0
[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
2020-10-13 12:02:26 -06:00
97c3bf7ea0
[Test] Add a test case for non-constant input multiplexers
2020-10-13 11:58:17 -06:00
c5bcd93408
[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
2020-10-13 11:57:21 -06:00
99b1e68d92
[Architecture] Add architecture using GND as constant inputs for multiplexers
2020-10-13 11:39:27 -06:00
570b494df7
[Test] Add test case for using GND signal as constant input for routing multiplexers
2020-10-13 11:38:54 -06:00
16128f0905
Merge pull request #107 from LNIS-Projects/dev
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Enable Customized Fabric Netlist Location in Verilog Testbench Generation
2020-10-12 13:47:40 -06:00
dc68c52d0a
[Test] Now use a light architecture to speed up the test case runtime
2020-10-12 12:53:34 -06:00
e59377a3ec
[Flow] bug fix in the sample script for fabric netlist customization
2020-10-12 12:52:01 -06:00
8941e38613
[Test] Enable verification in the new test case
2020-10-12 12:50:08 -06:00
9e1fd300dc
[Test] Add test case for customized location of fabric netlists
2020-10-12 12:47:58 -06:00
e510e79c12
[Flow] Add openfpga shell example script to use fabric netlist option
2020-10-12 12:42:43 -06:00
8493345b52
Merge pull request #105 from LNIS-Projects/dev
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Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
2020-10-10 21:43:02 -06:00
82e7b159ce
[Regression test] Add test case for fracturable LUT using AND gate to switch modes
2020-10-10 20:26:41 -06:00
d0014878d5
[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
2020-10-10 20:24:57 -06:00
521accdc88
Merge pull request #104 from lukefahr/disp_fix
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FLOW: fixed display flag
2020-10-07 09:54:06 -06:00
7b12c28e4f
Merge pull request #102 from lukefahr/blif_bug
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Fixed blif formatting bug
2020-10-06 20:05:02 -06:00
33bbe0ec48
FLOW: fixed display flag
2020-10-06 20:52:28 -04:00
d68427e47b
Fixed blif formatting bug
2020-10-06 20:46:50 -04:00
2d92a1f1af
Edits to enable basic run_fpga_flow.py
2020-10-02 10:18:10 -04:00
d4d02ab16a
[Regression Test] Move fabric key tests to basic tests
2020-09-29 14:22:23 -06:00
ff6570df9d
[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
2020-09-29 14:19:40 -06:00
4f00d310d3
[Architecture] Add example fabric key using multiple regions
2020-09-29 14:14:50 -06:00
02ea639959
[Regression Test] Add test for fabric key based on multiple region
2020-09-29 14:13:38 -06:00
a0d1d68402
[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
2020-09-29 13:53:41 -06:00
d5c7411399
[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
2020-09-29 13:50:31 -06:00
5be5835b71
[Regression Test] Add multiple region configuration chain test case
2020-09-29 13:48:39 -06:00
23449dc5c3
[Architecture] Add multiple region configuration chain architecture
2020-09-29 13:46:40 -06:00
e09e5fa6c6
[Architecture] Update fabric key for region syntax
2020-09-27 20:40:37 -06:00
ffd926d686
[Architecture] Update external bitstream
2020-09-25 21:30:59 -06:00
dcbd6a0614
[Architecture] Add lib name to TGATE to test compatibility
2020-09-25 21:08:12 -06:00
019208ec0f
[Architecture] Reorganize the cell netlists and update architecture files accordingly
2020-09-25 11:55:28 -06:00
20d6b2bf84
[Architecture] Remove out-of-date Verilog testbench
2020-09-24 21:14:13 -06:00
00bf775971
[Architecture] Bug fix for adder renaming
2020-09-24 20:54:18 -06:00
0a53a719bd
[Architecture] Bug fix due to adder renaming
2020-09-24 20:42:24 -06:00
e4bfa2ef51
[Architecture] Update external bitstream file
2020-09-24 20:16:50 -06:00
bd0f0144a0
[Architecture] Rename AIB architecture for the new cell naming
2020-09-24 20:14:16 -06:00
8edfc79f53
[Architecture] Rename AIB cell
2020-09-24 20:11:21 -06:00
4ada793c84
[Architecture] Adapt openfpga architecture to follow the renamed adder cell
2020-09-24 20:09:29 -06:00
53187044e6
[Architecture] Rename adder cell
2020-09-24 20:07:57 -06:00
4a0a448171
[Architecture] Rename openfpga architecture for the I/O cell
2020-09-24 19:56:01 -06:00
e0f9547f5b
[Architecture] Rework the i/o cell Verilog HDL
2020-09-24 19:53:54 -06:00
eb5fd1f44e
[Architecture] Bug fix for architectures using scan-chain DFF cell
2020-09-24 18:37:25 -06:00
60a14ccbd2
[Architecture] Bug fix in architectures that use BRAM
2020-09-24 18:20:55 -06:00
d51efd397f
[Architecture] Bug fix for architectures using DFF cells
2020-09-24 18:02:42 -06:00
3ade6d6ff5
[Architecture] Bug fix for dff that are used in data path
2020-09-24 17:53:30 -06:00
3e7c88eac8
[Architecture] Bug fix in Verilog netlist for scan-chain DFF
2020-09-24 17:41:03 -06:00
7494556316
[Architecture] Bug fix for scan-chain FF cell
2020-09-24 17:38:16 -06:00
54b3f244d3
[Architecture] Remove obsolete Verilog netlists
2020-09-24 17:35:02 -06:00
49d6863641
[Architecture] Bug fix for scan-chain FF cell renaming
2020-09-24 17:33:14 -06:00
0a5369f919
[Architecture] Adapt all the architecture files to use standard DFF cell
2020-09-24 17:26:48 -06:00
19dd3778d9
[Architecture] Add test case for memory bank to use both reset and set
2020-09-24 17:04:24 -06:00
335f5b78c1
[Regression Test] Add test case to use both set and reset for configuration frame
2020-09-24 17:02:28 -06:00
2d81ff9012
[Regression test] Add configuration chain test case where both set and reset are used
2020-09-24 16:59:52 -06:00
fc154b8560
[Architecture] Bug fix due to switching CCFF cell
2020-09-24 16:45:56 -06:00
79875d5a91
[Architecture] Bug fix in the configuration chain arch using both reset and set
2020-09-24 15:27:26 -06:00
9cb67e6097
[Architecture] Now all the configuration chain architecture use the DFFR cell by default
2020-09-24 15:19:37 -06:00
81965e75f6
[Architecture] Bug fix in DFF Verilog HDL
2020-09-24 14:53:21 -06:00
3b42fe94d6
[Architecture] Update external bitstream file
2020-09-24 14:41:44 -06:00
7fbccdd102
[Regression Tests] Add test cases for configuration chain using different DFF cells
2020-09-24 14:34:12 -06:00
178afb3c7f
[Architecture] Add configuration chain architectures using different DFF cells
2020-09-24 14:23:27 -06:00
98d88dc686
[Architecture] Bug fix for vanilla memory organization
2020-09-24 14:13:48 -06:00
efad0402c2
[Regression Test] Bug fix for CI errors
2020-09-24 13:55:41 -06:00
e7906899dd
[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
2020-09-24 13:53:12 -06:00
e832d806c7
[Architecture] Add DFF Verilog netlist using standard naming convention
2020-09-24 13:50:59 -06:00
1b13e8ecb1
[Architecture] Bug fix in the SRAM Verilog
2020-09-24 12:26:13 -06:00
ffd1a72d22
[Architecture] Add regression tests for the frame-based configuration using reset and set signals
2020-09-24 12:18:26 -06:00
539bb617f9
[Architecture] Add reset test case for frame based configuration
2020-09-24 12:17:18 -06:00
2add0406a7
[Architecture] Update architecture files for new latch naming
2020-09-24 12:14:03 -06:00
fde15c4f88
[Regression Test] Add test for fast memory bank configuration using set signals
2020-09-24 12:13:35 -06:00
7238a2be03
[Architecture] Merge latch Verilog HDL to a unique file
2020-09-24 11:02:01 -06:00
48083d2276
[Regression Test] Adapt fast memory bank test case
2020-09-24 10:32:03 -06:00
83971bba41
[Architecture] Update cell ports for native SRAM cell
2020-09-24 10:31:31 -06:00
186f00edfc
[Regression Test] Add test cases for memory bank using different SRAM cells
2020-09-24 10:25:03 -06:00
56c9aab190
[Architecture] Add architecture to use different SRAM cells for memory bank
2020-09-24 10:15:08 -06:00
6bb30ab33c
[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support
2020-09-24 10:02:51 -06:00
10b6e1dc0d
[Architecture] bug fix for active-low
2020-09-23 23:06:46 -06:00
5b0d451f0f
[Regression Test] Add test case for configurable latch with active-low set
2020-09-23 23:04:10 -06:00
5d60b4ef8c
[Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set
2020-09-23 23:02:49 -06:00
8e780635df
[Regression Test] Rename test case in CI
2020-09-23 22:59:46 -06:00
d0cef68242
[Regression test] Add test case for using resetb
2020-09-23 22:58:59 -06:00
c7fc0178b0
[Architecture] Rename to be consist with other architectures
2020-09-23 22:57:06 -06:00
707300a6e4
[Architecture] Bug fix for using both reset and set architecture
2020-09-23 22:07:40 -06:00
77a1f99564
[Architecture] Bug fix for architecture using set only
2020-09-23 22:04:24 -06:00
fcf1ff418f
[Architecture] Add Verilog for SRAM using set/reset
2020-09-23 21:53:38 -06:00
73e59d67af
[Architecture] Add test case for fast configuration using set signals
2020-09-23 21:50:23 -06:00
349aa79069
[Regression test] Add test case for smart fast configuration
2020-09-23 21:49:38 -06:00
9331ef941d
[Architecture] Add architecture that use both set and reset signals
2020-09-23 21:46:04 -06:00
7591060fbd
[Architecture] Add configurable latch Verilog designs and assoicated architectures
2020-09-23 21:45:06 -06:00
8fa4fa1125
[Architecture] Add openfpga architecture using set signals for configurable latch
2020-09-23 21:39:31 -06:00
05c2e652a4
[Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol
2020-09-23 20:44:06 -06:00
2869eae8a9
[Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol
2020-09-23 20:43:15 -06:00
fc60b18191
[Architecture] Now a regular flip-flop can be used in frame-based configuration
2020-09-23 20:41:49 -06:00
8e4e66038a
[Architecture] Bug fix for standalone memory
2020-09-23 19:32:48 -06:00
129caea38c
[Architecture] Patch configurable latch Verilog HDL with resetb
2020-09-23 18:30:48 -06:00
1864b080a2
[Architecture] Bug fix in configurable latch Verilog HDL
2020-09-23 18:28:45 -06:00
ebb866d04a
[Architecture] Patch frame based using ccff
2020-09-23 18:04:14 -06:00
906191e931
[Architecture] Use strict latch Verilog HDL in frame-based procotol
2020-09-23 17:58:13 -06:00
645db17168
[Architecture] Patch DFF Verilog HDL
2020-09-23 17:52:59 -06:00
092ada39f4
[Architecture] Add Verilog HDL for DFF with write enable
2020-09-23 17:49:30 -06:00
ad385c6d69
[Regression Test] Add test case for using SRAM cell in frame-based configuration
2020-09-23 17:39:36 -06:00
1a2c66f07d
[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
2020-09-23 17:34:49 -06:00
a3c982a83f
[Architecture] Patch the openfpga architecture using active-low configurable latch
2020-09-23 17:27:16 -06:00
f23c25e123
[Regression Test] Add test case for configurable latch with active-low reset
2020-09-23 17:25:17 -06:00
a94c2655c2
[Architecture] Patch Verilog HDL for configurable latch
2020-09-23 17:21:30 -06:00
893859be37
[Architecture] Add openfpga architecture using active-low configurable latch
2020-09-23 17:21:00 -06:00
b242ab79bd
[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset
2020-09-23 17:19:02 -06:00
149d5b20bd
[Regression Test] Add test case for fixed device support
2020-09-23 16:47:11 -06:00
c92cf71891
[Regression Test] Add a new template script for fixed device support
2020-09-23 16:46:41 -06:00
3350695806
[Regression test] Add test case for pattern based local routing architecture
2020-09-23 16:06:47 -06:00
1aab691e9d
[Architecture] Add openfpga architecture using pattern based local routing
2020-09-23 16:06:16 -06:00
951a47b19c
[Architecture] Add k4 series architecture using pattern-based local routing
2020-09-23 16:05:39 -06:00
7729f671ab
[Regression Tests] Remove deadlink
2020-09-22 18:35:41 -06:00
51c0319657
[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
2020-09-22 15:32:54 -06:00
70b8b02f74
[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
2020-09-22 15:32:11 -06:00
72749be4bd
[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
2020-09-22 15:31:34 -06:00
61bcbaafd8
[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
2020-09-22 15:15:19 -06:00
3d1f49fb2f
[Regression Test] Add testcase for k4n4 with multiple segments
2020-09-22 12:47:41 -06:00
13df6c1c21
[Architecture] Add openfpga architecture for k4n4 using multiple segments
2020-09-22 12:36:11 -06:00
8a3934b749
[Architecture Add vpr architecture for k4n4 using multiple wire segments
2020-09-22 12:35:39 -06:00
5741664580
[Regression Test] Add test case for k4n4 bram architecture
2020-09-22 12:23:56 -06:00
ddf999b6b9
[Architecture] Add verilog HDL for dual-port BRAM 1k
2020-09-22 12:23:28 -06:00
26fba4a94b
[Architecture] Add openfpga architectue for k4n4 with bram blocks
2020-09-22 12:22:59 -06:00
daf776b7b1
[Architecture] Add k4n4 architecture with bram block for basic tests
2020-09-22 12:22:32 -06:00
3bf94b8e34
[Regression test] Remove no local routing from fpga verilog tests
2020-09-22 11:48:19 -06:00
7ed9f76b06
[Regression test] Move k4n4 no local routing to basic test
2020-09-22 11:47:03 -06:00
2dea97afb6
[Regression test] reduce runtime for k4n4 test in basic testing
2020-09-22 11:45:29 -06:00
ea4dd410b7
[Regression Test] Add k4n4 fracturable lut test case to basic test
2020-09-22 11:41:36 -06:00
dad19cac9a
[Regression test] Add k4 series architecture: fracturable adder
2020-09-22 11:39:18 -06:00
dd192a2f54
[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
2020-09-22 11:34:23 -06:00
7a6f5a06f7
[Architecture] Add a k4n4 architecture with carry chain to quick test
2020-09-22 11:33:56 -06:00
aa5f5fc7e0
[Architecture] Bring back pin equivalence for no local routing architecture
2020-09-21 22:22:39 -06:00
a8a269aa82
[Architecture] Temporary patch for the no local routing architecture
2020-09-21 19:51:23 -06:00
acf318f184
[Regression test] Bug fix in test case fabric_chain
2020-09-21 18:58:35 -06:00
e4291eb27e
[Regression Tests] Now use fixed device layout in test cases for best coverage
2020-09-21 18:44:13 -06:00
7a57cc9cf4
[Architecture] A new device layout to k4n4 to test untileable architecture
2020-09-21 18:36:50 -06:00
2bbfcb5753
[Architecture] Add a new device layout to k4n4 for testing tileable routing
2020-09-21 18:34:31 -06:00
e1c5947143
[Architecture] Add auto layout and fixed layout to architectures
2020-09-21 18:01:51 -06:00
936a164eee
[OpenFPGA flow] Add a new template script to use a fixed device layout
2020-09-21 17:48:28 -06:00
d7f8b3abad
[Architecture] Add k4 N4 untilable architecture
2020-09-21 17:44:37 -06:00
a83bc3f75c
[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
2020-09-21 17:38:16 -06:00
e9c0e90544
[Architecture] Add a VPR architectue using fracturable LUT4
2020-09-21 17:37:26 -06:00
60f328a2ab
[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
2020-09-21 17:36:57 -06:00
681e80d4b6
[Regression tests] update frac_lut test case using more representative benchmarks
2020-09-17 10:39:22 -06:00
367cf59efd
[Benchmark] Bug fix in the and2_or2 benchmark
2020-09-17 10:35:13 -06:00
de48b8c7b2
[Benchmark] Add a new micro benchmark to test fracturable LUTs
2020-09-17 10:21:25 -06:00
ca1bafc688
[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
2020-09-16 19:26:12 -06:00
c22d8e2421
[Architecture] Bug fix in no local routing architecture
2020-09-16 18:07:52 -06:00
c40c9f5876
[Regression test] add test case for no local routing architecture
2020-09-16 18:05:33 -06:00
f5b7ac6269
[OpenFPGA Architecture] Add a new architecture with no local routing
2020-09-16 18:04:55 -06:00
35d47ee0e7
[Regression tests] bug fix in the test case for fully connected output crossbar
2020-09-16 17:33:54 -06:00
030d7f02f8
[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
2020-09-16 17:30:08 -06:00
30fb99095f
[Regression Tests] Add new test case for fully connected output crossbar
2020-09-16 17:29:15 -06:00
3c0faf0021
[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
2020-09-16 17:27:24 -06:00
f42411c29e
[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
2020-09-14 16:03:43 -06:00
aaf63050bb
[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
2020-09-14 15:58:34 -06:00
aa9521b23b
[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
2020-09-14 15:57:44 -06:00
eecfd186f0
[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
2020-09-14 15:46:10 -06:00
9bf0e772a3
[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
2020-09-14 15:45:35 -06:00
4b3142c4ee
[Architecture File] Patch openfpga architecture with default circuit model definition
2020-08-23 15:13:28 -06:00
9101ba1021
[Architecture Language] Update openfpga architecture files for default models
2020-08-23 14:55:44 -06:00
6c925dcded
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 20:11:37 -06:00
881672d46a
update thru channel arch for avoid buggy pin locations
2020-08-19 19:52:35 -06:00
bf08e1841c
add new test case using thru channels
2020-08-19 17:58:34 -06:00
f0bc6f83f1
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
2020-08-19 15:34:59 -06:00
18735894f9
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
2020-08-19 15:27:30 -06:00
3273f441fe
bug fix in the flagship vpr arch
2020-08-19 15:23:20 -06:00
aa4a9b28cc
start testing the initial offset in the flagship architecture
2020-08-19 15:03:46 -06:00
f64079641d
bug fix in flagship vpr arch with frac mem and dsp
2020-08-19 12:43:58 -06:00
d7efdf35b6
add custom pin location to the flagship vpr arch with frac mem and dsp
2020-08-19 11:15:25 -06:00
dbd93e429d
now pro_blif.pl can accept customized clock name
2020-08-19 09:43:44 -06:00
743167521a
add Verilog design for fracturable 32k memory
2020-08-18 21:13:46 -06:00
42b5ea2cb1
bug fix in openfpga arch for frac mem and dsp
2020-08-18 20:42:36 -06:00
3ee4e10aa8
bug fix in the frac mem & DSP vpr arch
2020-08-18 17:25:45 -06:00
098859fe06
bug fix in the frac memory & DSP architecture
2020-08-18 15:05:51 -06:00
21c7eaa9cf
add 36-bit fracturable multiplier Verilog
2020-08-18 14:06:08 -06:00
f833e0ec66
add a flagship architecture using fracturable memory and dsp
2020-08-17 17:49:51 -06:00
1ca2829868
update readme for vpr architecture naming
2020-08-17 13:54:26 -06:00
cadf29022e
add README to explain the organization of regression tests
2020-07-28 13:44:06 -06:00
f33422d4d7
add regression test to track runtime on big fpga devices using practical benchmarks
2020-07-28 12:38:42 -06:00
534c609e17
add fixed layouts to a flagship architecture to test bitstream generation runtime
2020-07-28 11:51:50 -06:00
a156807559
enrich basic regression tests to cover more critical microbenchmarks
2020-07-27 19:47:43 -06:00
5d83abb2cf
bug fix in read architecture bitstream and regression tests
2020-07-27 19:37:05 -06:00
31e7a753a6
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-27 19:22:16 -06:00
747c062f86
BugFix : Flow script accepts extra OpenFPGA arguments
2020-07-27 18:10:43 -06:00
50cc4dfba3
classify regression test to dedicated categories
2020-07-27 17:18:59 -06:00
5595ee9052
refine the test case for load external arch bitstream
2020-07-27 16:53:29 -06:00
cec6bf0b6f
add or2 microbenchmark for testing external arch bitstream
2020-07-27 15:59:03 -06:00
4174fbf77d
add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
2020-07-27 15:54:46 -06:00
a3eba8acbe
update task files using the new syntax on SHELL variables
2020-07-27 15:25:49 -06:00
615b557dc4
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-27 14:48:23 -06:00
dc7012d590
update regression tests for split fabric_bitstream commands
2020-07-27 14:24:48 -06:00
45af056304
TASK_NAME and TASK_DIR variables are avaialble in config file now
2020-07-27 14:14:57 -06:00
0e46e0d857
Updated task.conf format to have transparent shell variables
2020-07-27 14:08:58 -06:00
177de90822
bug fix in example scripts
2020-07-26 22:10:04 -06:00
f687774452
bug fix in template scripts
2020-07-26 21:46:03 -06:00
41a76126b9
add fabric bitstream writer to CI
2020-07-26 21:44:42 -06:00
c87f6b75b9
add test case for FPGA-SPICE
2020-07-24 19:12:35 -06:00
020154b0cd
add depopulate crossbar test case
2020-07-24 18:06:02 -06:00
021fedbc12
update fabric key to synchronize with new module/instance naming
2020-07-24 12:55:40 -06:00
fefcd88f14
update openfpga architecture README for power-gating
2020-07-22 21:55:59 -06:00
22159531c5
bug fix in power gating support of FPGA-Verilog
2020-07-22 20:21:38 -06:00
ca867ea6fa
add power gate inverter test case (full testbench)
2020-07-22 20:09:52 -06:00
87ef7f9f99
add power gate example architecture
2020-07-22 20:06:10 -06:00
8ade40713a
add missing architecture for CI
2020-07-22 14:07:39 -06:00
1a1c3885e7
use k6 n10 in mux designs to speed up CI
2020-07-22 13:54:09 -06:00
95c1fe61e1
use k6 n8 in mux design to speed up CI
2020-07-22 13:49:03 -06:00
f754c8af06
use k6_n10 architecture to reduce CI runtime
2020-07-22 13:45:55 -06:00
92c3449999
bug fix in the regression test due to benchmark changes
2020-07-22 13:17:05 -06:00
05dccadf21
bug fix in the testcases using yosys_vpr flow
2020-07-22 12:44:19 -06:00
7d39e136a4
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
1d36de817f
adapt generate bitstream testcase to use yosys vpr flow
2020-07-22 12:24:34 -06:00
b96cdbf857
adapt preconfig test cases to use yosys_vpr flow
2020-07-22 12:23:39 -06:00
d8804f4ec1
deploy yosys_vpr flow to basic regression tests
2020-07-22 12:21:59 -06:00
f4e77e3bad
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-22 12:09:34 -06:00
3b6cd885f3
BugFix: Fixed yosys_vpr with openFPGA_Shell
2020-07-22 11:57:04 -06:00
eb070694b5
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
2020-07-15 17:52:41 -06:00
ca90f337a7
add fast configuration chain test case
2020-07-15 11:56:47 -06:00
66a50742fc
use configuration chain in the k4k4 test case to speed up CI
2020-07-15 11:56:11 -06:00
1c5bede282
update arch file with device technology binding information
2020-07-13 19:06:51 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
1e6955aaa4
rename arch directory to be clear for its usage
2020-07-04 19:13:28 -06:00
f9a2bb0490
Reorganize task directory
2020-07-04 19:06:41 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
1c634e4600
add missing task file for generate bitstream test case
2020-07-02 17:24:51 -06:00
adea6fcec4
add bitstream generation only test case to CI
2020-07-02 16:31:22 -06:00
73e75bf456
add readme for OpenFPGA architecture naming
2020-07-01 10:27:21 -06:00
20cf4acda0
add readme for architecture file naming
2020-07-01 09:54:13 -06:00
b2fb5f760c
update sample key
2020-06-27 15:01:12 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
3d56cd3060
fine tuning on the script for MCNC benchmarks
2020-06-15 20:09:46 -06:00
0d81f60fd8
add new options to openfpga task configuration files
2020-06-12 19:48:39 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
2d35848cfa
add external key test cases
2020-06-12 13:11:21 -06:00
65b387a589
develop test cases for fabric keys
2020-06-12 11:32:52 -06:00
cf9c3b0f44
add write fabric to test cases
2020-06-12 10:50:23 -06:00
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
068d9943e7
update all the templates and regression test cases with simulation settings
2020-06-11 19:31:16 -06:00
1842bf51e1
deploy read_openfpga_simulation_setting in CI on a single test case
2020-06-11 19:31:16 -06:00
cb09896f23
add example simulation setting for openfpga flow
2020-06-11 19:31:15 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
c87dbc4880
start using counter benchmark in regression tests
2020-06-11 19:31:15 -06:00
f73dfa2bcc
bug fixed in k6_n10_40 architecture
2020-06-11 19:31:15 -06:00
baa2c6b7ef
update arch to support reset signal for SRAm
2020-06-11 19:31:14 -06:00
aac2e8c805
update openfpga architecture for memory bank usage
2020-06-11 19:31:14 -06:00
82b04ae3f0
add SRAM verilog for memory bank usage
2020-06-11 19:31:14 -06:00
3f9afea3e8
add preconfig testbench test case for memory bank configuration protocol
2020-06-11 19:31:14 -06:00
288294c23a
add fast configuration test case for memory bank configuration protocol
2020-06-11 19:31:14 -06:00
73d4c835b7
add regression test case for memory bank
2020-06-11 19:31:13 -06:00
a1ec6833c2
add memory bank example arch xml
2020-06-11 19:31:13 -06:00
2def059b5b
add standalone configuration protocol to pre config test cases
2020-06-11 19:31:12 -06:00
5f6a790eff
add new test cases for the standalone memory configuration protocol
2020-06-11 19:31:12 -06:00
8b5b221a21
add new architecture for standalone memory organization
2020-06-11 19:31:12 -06:00
a5138113e4
add fast configuration testcase
2020-06-11 19:31:12 -06:00
8b3e79766c
add fast configuration option to fpga_verilog to speed up full testbench simulation
2020-06-11 19:31:12 -06:00
05aa166a9e
add preconfig testbench cases to regression tests for different configuration protocols
2020-06-11 19:31:11 -06:00
827e2e6713
file moving in regression tests
2020-06-11 19:31:11 -06:00
b5e5182f52
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
2020-06-11 19:31:11 -06:00
583c15131b
change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
2020-06-11 19:31:11 -06:00
6a72c66eb8
bug fixed for frame-based configuration memory in top-level full testbench
2020-06-11 19:31:11 -06:00
f5968fda52
add configurable latch Verilog codes
2020-06-11 19:31:10 -06:00
1e73fd6def
create configuration frame example script
2020-06-11 19:31:10 -06:00
3a0d3b4e95
fix the broken CI/regression tests due to incorrect file path
2020-06-11 19:31:10 -06:00
3fa3b17061
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
2020-06-11 19:31:10 -06:00
bba476fef4
add explicit port mapping support to Verilog testbench generator
2020-06-11 19:31:07 -06:00
910be3cadb
massively deploy disable_timing for configure ports in CI
2020-06-11 19:31:06 -06:00
13f591cacf
add new command to disable timing for configure ports of programmable modules
2020-06-11 19:31:06 -06:00
fc2b09514e
add configuration chain write to regression tests
2020-06-11 19:31:06 -06:00
1943929353
add write_fabric_hierarchy to regression tests
2020-06-11 19:31:04 -06:00
98fbcb5410
add time unit test for SDC generation to CI
2020-06-11 19:31:04 -06:00
4083fae41a
add new test cases about user-defined simulation settings
2020-06-11 19:31:03 -06:00
2fbf9c2cfc
change to a higher simulation clock speed to accelerate CI verification.
...
Later, we should place simulation information in another XML so that we can reuse that easily
2020-06-11 19:31:03 -06:00
889bc8dbe8
add more test cases about LUT design and deploy to CI
2020-06-11 19:31:02 -06:00
889f179ce7
add local encoder test case
2020-06-11 19:31:01 -06:00
98a658a013
bug fixed in routing_test.v. Deployed to regression tests
2020-06-11 19:31:01 -06:00
6dd8d347e1
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
2020-06-11 19:31:01 -06:00
f6cea1e17c
Added test_mode_low benchmark
2020-06-11 19:31:01 -06:00
3c781b18d3
Added routing benchmark
2020-06-11 19:31:01 -06:00
42cede37fa
add testcases on generate fabric/testbench only
2020-06-11 19:31:01 -06:00
9bf91bd92a
start testing mcnc_big20 using OpenFPGA tasks
2020-06-11 19:30:55 -06:00
c31b20dc91
Added support for simulation setting file in the task flow
2020-06-11 19:28:13 -06:00
49edeb119c
BugFix : Relative path for refrence benchmark fixed
2020-06-11 19:28:13 -06:00
890ead91b9
Fixed modelsim include references
2020-06-11 19:28:13 -06:00
c1b73efa62
Added support for simulation setting file in the task flow
2020-06-10 23:12:30 -06:00
a3103f6afe
BugFix : Relative path for refrence benchmark fixed
2020-04-25 20:16:17 -06:00
9d1b3d6865
Fixed modelsim include references
2020-04-24 21:53:57 -06:00
90f608baea
changing task mcnc file for debugging (temporarily now) Will be corrected later
2020-04-23 18:58:39 -06:00
417d534121
fine tune mcnc example script to run Modelsim simulations easily
2020-04-23 16:15:45 -06:00
df85175765
fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
2020-04-22 21:44:52 -06:00
f9fcc6b471
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
2020-04-22 18:24:09 -06:00
726185cd5e
add test cases using spypad architecture
2020-04-22 12:56:57 -06:00
73e9006372
add arch file with spy pads
2020-04-22 12:56:09 -06:00
9fb8971281
add FPGA arch with spypads to portofilo
2020-04-22 11:12:28 -06:00
9761d13eef
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
489ca75230
adapt benchmark and_latch module name to be different than benchmark and
2020-04-20 13:15:05 -06:00
f6b7583a2a
add tasks for single mode
2020-04-20 12:55:40 -06:00
8b03ec900f
fine-tune micro benchmark to fit port mapping in testbenches
2020-04-19 17:05:12 -06:00
e10cafe0a5
Critical patch on repacking about wire LUT support.
...
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
32ed609238
update micro benchmark set and regression tests using them
2020-04-19 12:49:07 -06:00
98878f474b
light change on arch file to accelerate mcnc big20 run
2020-04-19 12:03:31 -06:00
cc163081f5
recover mcnc big20 test configuration
2020-04-18 21:06:43 -06:00
2e3a811f4f
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
2020-04-18 21:04:46 -06:00
f76a3090c4
add mcnc big20 test cases and start debugging
2020-04-18 19:25:16 -06:00
95863e996a
minor update on arch to use auto layout sizing
2020-04-18 18:43:56 -06:00
2f3a36ee81
update timing and rename the arch file
2020-04-18 18:39:47 -06:00
7ce34be175
update sample architecture timing
2020-04-17 22:06:06 -06:00
2ea4b8a2a2
add more flagship architectures
2020-04-17 19:12:27 -06:00
2ffd174e6a
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
2020-04-15 15:48:33 -06:00
032ebc29e6
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-04-15 12:53:20 -06:00
1e742a3676
add test case on auto-check test benches
2020-04-15 12:52:52 -06:00
689c4a3e19
BugFix: The filename in the previous commit
2020-04-15 12:44:22 -06:00
46fe1e84ce
Merge branch 'dev' into ganesh_dev
2020-04-15 12:27:51 -06:00
7f37bf1441
Added formal verification support to fpga_flow script
2020-04-15 12:24:51 -06:00
7ba3e27371
add duplicated_grid_pin test case to Travis CI
2020-04-12 20:10:51 -06:00
e78643f108
add flatten routing test case to Travis CI
2020-04-12 20:06:40 -06:00
59ea0a6ad5
add implicit verilog test case to Travis CI
2020-04-12 20:00:20 -06:00
23aef96d3a
add behavioral verilog test case to Travis CI
2020-04-12 19:55:47 -06:00
11e9014542
add notes about debugging the aib FPGA
2020-04-12 19:07:53 -06:00
a614e5aad9
add long adder chain to Travis CI
2020-04-12 15:43:19 -06:00
f71a85a1d4
add test cases on different routing multiplexer circuit designs to Travis CI
2020-04-12 15:39:45 -06:00
214d98fbcd
add register chain and scan chain to Travis CI
2020-04-12 15:28:22 -06:00
148cc74d6a
add io test cases to Travis CI
2020-04-12 15:01:47 -06:00
da5af8f0e0
try to add aib test case. bug found
2020-04-12 14:54:45 -06:00
28cb412359
add test case of wide BRAM 16k to Travis CI
2020-04-12 14:37:08 -06:00
5d665aa04b
reshape bram test case
2020-04-12 14:32:09 -06:00
600a48edc7
add test case of BRAM to Travis CI
2020-04-12 14:27:05 -06:00
2444752de8
add untileable test case to Travis CI
2020-04-12 14:08:24 -06:00
d806ad3148
add testcases using openfpga_shell in openfpga_flow
2020-04-12 12:54:21 -06:00
68fd296e14
add more test vpr architecture to regression tests
2020-04-12 12:49:16 -06:00
80bdb41df6
Updated task file to run formal verification
2020-04-11 18:30:21 -06:00
49ddbf98c3
add more testing architecture to openfpga_flow
2020-04-11 18:01:09 -06:00
130b78ca74
update arch in openfpga_flow
2020-04-11 18:00:37 -06:00
f6b3c5854a
Bugfix :
...
+ OpenFPGA template variables update
+ Default path for the verilog netlist
2020-04-11 16:45:22 -06:00
8ea272dc2c
Patched the OpenFPGA shell execution bug
2020-04-08 21:28:14 -06:00
583a4d8767
Fixed bug in openfpga_flow script
2020-04-08 12:04:08 -06:00
e1db4df744
Created task for FPGA shell run
2020-04-06 00:35:07 -06:00
ea4122a8a4
Updated openfpga_flow and task file to support sheel run
2020-04-06 00:34:36 -06:00
7f98ecc8a6
OpenFPGA shell run test script template
2020-04-06 00:32:43 -06:00
eb3b02277a
Added XML and benchmarks for testing
2020-04-06 00:32:06 -06:00
77f7e13ba7
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-04-05 20:59:10 -06:00
d1d3446568
backedup partial upgrade for fpga_flow script
2020-04-05 11:36:24 -06:00
2f38b5cbc2
Merge branch 'refactoring' into dev
2020-03-08 16:23:20 -06:00
b219b096ee
hotfix on removing dangling inputs from GSB, which are CLB direct output
2020-03-08 13:54:49 -06:00
c51001c853
Add compilation verification task in openfpga_flow
2020-01-23 13:13:23 -07:00
cd69f1870d
Merge remote-tracking branch 'origin/ganesh_dev' into dev
2020-01-23 10:07:36 -07:00
46bb5ef9d0
Added disp option in openfpga_flow, Default is --nodisp
2020-01-23 10:04:38 -07:00
85c9f26a9f
Update documentation about cmake version and graphical interface
2020-01-22 20:46:49 -07:00
f0bed1244c
Added blif file folding before VPR run
2020-01-09 16:50:34 -07:00
74b650e9e1
Added fpga_x2p_duplicate_grid_pin option
2019-12-30 12:25:28 -07:00
d1e260f54f
Spice related option added
2019-12-30 12:16:04 -07:00
ef9ed2ccbc
added duplicate_grid_pin test case
2019-12-26 15:08:31 -07:00
09fd2afa9c
Adding heterogeneous synthesis requirements
2019-12-03 16:09:26 -07:00
32176eb352
Adding EPFL benchmark task for openfpga_flow
2019-12-03 14:31:53 -07:00
2f14716f13
Adding DPRAM behavioural Verilog netlist and its TB
2019-12-03 13:58:20 -07:00
96733f9ea8
add minor comments in task file for modelsim regression tests
2019-11-16 22:34:03 -07:00
3f235a16f9
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2019-11-16 19:14:34 -07:00
6bb11918dc
Updated modelsim and collected result
2019-11-16 19:10:04 -07:00
a13f406918
tweaking mcnc_big20 task run for modelsim
2019-11-16 18:00:55 -07:00
00ec36c1af
Added Modelsim error check in log
2019-11-16 13:18:13 -07:00
373dbe0718
First draft for multithreaded Modelsim simulation
2019-11-16 01:06:09 -07:00
f05aede868
Added task support for modelsim script
2019-11-15 23:23:15 -07:00
f52eaef622
Updated flow script and skipped travis upload on failure test setup.
2019-11-15 14:35:15 -07:00
4df6402241
add python script for batch simulations
2019-11-15 14:23:03 -07:00
d391983e8c
passing regression test on dpram benchmarks
2019-11-07 14:57:46 -07:00
56b4ee008e
add test for heterogeneous FPGA and fix bugs
2019-11-06 17:45:11 -07:00
4ea5756be6
bug fixed for std cell MUX2 architecture and add the case to regression tests
2019-11-06 16:06:47 -07:00
09eb373a6e
bug fixing for autocheck top testbench where clock port is not default names
2019-11-06 12:21:20 -07:00
00280b835e
reorganize regression tests
2019-11-05 16:31:42 -07:00
7952d134b9
add tree-like mux test case to regression test
2019-11-05 16:24:39 -07:00
a308a13d7c
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
2019-11-05 15:41:59 -07:00
0ec465d4e1
refactoring auto-check top Verilog testbench
2019-11-03 17:41:29 -07:00
dc241e6c03
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
2019-11-02 23:03:47 -06:00
a880802803
Bug Fix: Corrected read VPR stat filename
2019-11-01 20:51:05 -06:00
e2b042c61c
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
2019-11-01 18:27:27 -06:00
370a5ed408
Bug Fix: shifter ff.v include path to tcl script
2019-11-01 18:22:40 -06:00
595d2d3070
Simple argument shuffle
2019-11-01 18:21:26 -06:00
27005d6640
Added Modelsim Python Script
2019-11-01 18:20:40 -06:00
49bfb3223c
add compact routing to regression test
2019-11-01 10:53:47 -06:00
531cc064fc
bug fixing for formal top-level testbench
2019-11-01 10:47:40 -06:00
da0778e813
Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
2019-11-01 00:46:34 -06:00
d709868463
adding more regression tests which is quick run but very helpful for debugging
2019-10-31 20:17:40 -06:00
a6a3e7c36b
adding mcnc_big20 to regression test
2019-10-31 19:31:27 -06:00
81180939ca
Bug fix: Missing exit_if_fail flag in fpga_flow script
2019-10-31 09:56:57 -06:00
5531422186
update regression test with no-explicit port mapping cases
2019-10-30 19:37:06 -06:00
55fbd72293
many bugs have been fixed
2019-10-30 15:50:42 -06:00
4398cffaaa
single mode is working, multi-mode is under debugging
2019-10-29 22:32:36 -06:00
10491c4291
bring single mode test case online with bug fixing
2019-10-28 17:04:10 -06:00
5cb3717433
add single mode test case to regression test. debugging now
2019-10-28 15:57:17 -06:00
c034b871bb
Made activity file independent of power option
2019-10-15 16:08:25 -06:00
eaf8ecee86
added _vpr.txt subscript to vpr log files
2019-10-15 16:07:34 -06:00
027272c976
Faster regression test
2019-10-05 12:10:55 -06:00
db059af8b8
Lighten the regression test
2019-10-03 13:33:28 -06:00
c7e1f7d90b
Added explicit_verilog to regression test in a clean way
2019-10-03 10:17:04 -06:00
33e50bbc8c
fix
2019-10-01 16:54:16 -06:00
7c3ab38410
Hot fix
2019-10-01 16:40:16 -06:00
069f628bb0
Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
2019-09-28 11:21:37 -06:00
d269472daf
Updated formality python script
2019-09-27 14:00:57 -06:00
feddcbcb21
Merge remote-tracking branch 'origin/dev' into heterogeneous
2019-09-23 11:41:38 -06:00
5efea159c5
Simplify part of regression test to min_route_chan_width
2019-09-22 11:14:33 -06:00
1dffe54807
Merge remote-tracking branch 'origin/ganesh_dev' into dev
2019-09-22 00:21:25 -06:00
50039a4b6e
Added remove run directory option
2019-09-21 23:35:56 -06:00
cc0bfdd548
Add testcase in regression test for architecture with 1 IO cell/IO block
2019-09-20 10:27:26 -06:00
4e7af5cdc5
update tileable_routing test
2019-09-18 15:59:32 -06:00
0f0d06aad7
add non-LUT intermediate buffer to test and apply minor bug fix
2019-09-18 15:04:51 -06:00
8afcba2c45
Merge remote-tracking branch 'origin/ganesh_dev' into dev
2019-09-18 12:15:42 -06:00
cd5fd6ce6c
Added explicit checking to VVP execution
2019-09-18 12:14:26 -06:00
56c40ca06d
Merge remote-tracking branch 'origin/ganesh_dev' into dev
2019-09-17 22:12:11 -06:00
169732ccc1
Added verbose option in VVP output
2019-09-17 22:09:37 -06:00
d7ac7d3649
start refactoring the switch block verilog generation
2019-09-17 20:40:26 -06:00
7be83235a0
Merge remote-tracking branch 'origin/ganesh_dev' into dev
2019-09-16 21:25:26 -06:00
678e3181ba
Made compact_routing_hierarchy options uncond
2019-09-16 21:22:13 -06:00
tangxifan
Tarachand Pagarani
ganeshgore
Lalit Sharma
Lalit Narain Sharma
Nachiket Kapre
AurelienAlacchi
Laboratory for Nano Integrated Systems (LNIS)
Andrew Lukefahr
CHARAS SAMY
AurelienUoU
Baudouin Chauviere