riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

bug fix in power gating support of FPGA-Verilog

This commit is contained in:
tangxifan 2020-07-22 20:21:38 -06:00
parent ca867ea6fa
commit 22159531c5
2 changed files with 5 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -45,18 +45,15 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
/* Create a sensitive list */
fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
fp << "\talways @(" << std::endl;
fp << "\talways @(";
/* Power-gate port first*/
for (const auto& power_gate_port : power_gate_ports) {
/* Only config_enable signal will be considered */
if (false == circuit_lib.port_is_config_enable(power_gate_port)) {
continue;
}
/* Skip first comma to dump*/
if (0 < &power_gate_port - &power_gate_ports[0]) {
fp << ",";
}
fp << circuit_lib.port_prefix(power_gate_port);
fp << ", ";
}
fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl;
@ -78,7 +75,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
/* Power-gated signal are disable during operating, enabled during configuration,
* Therefore, we need to reverse them here
*/
if (0 == circuit_lib.port_default_value(power_gate_port)) {
if (1 == circuit_lib.port_default_value(power_gate_port)) {
fp << "~";
}

4
openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
View File

@ -36,8 +36,8 @@
<design_technology type="cmos" power_gated="true" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="en" size="1" is_global="true" default_val="0" config_enable="true"/>
<port type="input" prefix="enb" size="1" is_global="true" default_val="1" config_enable="true"/>
<port type="input" prefix="en" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="enb" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12