From 22159531c5c1606b37096dd4b3238a6add6bd647 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Jul 2020 20:21:38 -0600
Subject: [PATCH] bug fix in power gating support of FPGA-Verilog

---
 openfpga/src/fpga_verilog/verilog_essential_gates.cpp    | 9 +++------
 .../k4_N4_40nm_powergate_frame_openfpga.xml              | 4 ++--
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
index 4893b5f49..d33407071 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
@@ -45,18 +45,15 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
   /* Create a sensitive list */
   fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
 
-  fp << "\talways @(" << std::endl;
+  fp << "\talways @(";
   /* Power-gate port first*/
   for (const auto& power_gate_port : power_gate_ports) {
     /* Only config_enable signal will be considered */
     if (false == circuit_lib.port_is_config_enable(power_gate_port)) {
       continue;
     }
-    /* Skip first comma to dump*/
-    if (0 < &power_gate_port - &power_gate_ports[0]) {
-      fp << ",";
-    }
     fp << circuit_lib.port_prefix(power_gate_port);
+    fp << ", ";
   }
   fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; 
 
@@ -78,7 +75,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
       /* Power-gated signal are disable during operating, enabled during configuration,
        * Therefore, we need to reverse them here   
        */
-      if (0 == circuit_lib.port_default_value(power_gate_port)) {
+      if (1 == circuit_lib.port_default_value(power_gate_port)) {
         fp << "~";
       }
       
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
index 567e7775f..bf96e1aa0 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
@@ -36,8 +36,8 @@
       <design_technology type="cmos" power_gated="true" topology="inverter" size="1"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="en" size="1" is_global="true" default_val="0" config_enable="true"/>
-      <port type="input" prefix="enb" size="1" is_global="true" default_val="1" config_enable="true"/>
+      <port type="input" prefix="en" size="1" is_global="true" default_val="0" is_config_enable="true"/>
+      <port type="input" prefix="enb" size="1" is_global="true" default_val="1" is_config_enable="true"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
         10e-12