bug fix in the testcases using yosys_vpr flow
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7d39e136a4
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05dccadf21
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,14 +23,11 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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@ -23,11 +23,9 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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@ -23,12 +23,10 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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@ -23,12 +23,10 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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@ -23,12 +23,10 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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@ -23,12 +23,10 @@ external_fabric_key_file=
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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