enrich micro benchmarks
This commit is contained in:
tangxifan
parent
1d36de817f
commit
7d39e136a4
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@ -0,0 +1,81 @@
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module FSM_hour(
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input wire rst,
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input wire clk,
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input wire [5:0] hour_in,
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input wire hour_in_load,
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input wire [5:0] min_count,
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input wire [5:0] sec_count,
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output reg [5:0] hour_out);
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reg [2:0] ps, ns;
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wire [5:0] hour_data_add;
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reg [5:0] hour_data;
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reg [5:0] hour_ps, hour_ns;
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reg [1:0] hour_sel;
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wire hour_count;
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always@(posedge clk)
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begin
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if(rst) ps <= 3'd0;
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else ps <= ns;
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end
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always@(posedge clk)
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begin
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if(rst) hour_ps <= 6'd0;
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else hour_ps <= hour_ns;
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end
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always@(*)
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begin
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hour_sel = 2'd0;
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case(ps)
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3'd0: begin
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ns = 3'd1;
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end
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3'd1: begin
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if(hour_in_load) begin
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hour_sel = 2'd1;
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hour_out = hour_data;
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ns = 3'd2;
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hour_ns = hour_data;
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end
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else ns = 3'd1;
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end
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3'd2: begin
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if(hour_count == 1'd1) begin
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if(hour_data == 6'd59) begin
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hour_out = hour_data;
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ns = 3'd2;
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hour_ns = 6'd0;
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end
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else begin
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hour_out = hour_data;
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ns = 3'd2;
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hour_ns = hour_data_add;
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end
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end
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else begin
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hour_out = hour_data;
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hour_ns = hour_data;
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ns = 3'd2;
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end
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end
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default: begin
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ns = 3'd0;
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end
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endcase
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end
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assign hour_data_add = hour_data + 1;
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assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0;
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always@(*)
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begin
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case(hour_sel)
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2'd0: hour_data = hour_ps;
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2'd1: hour_data = hour_in;
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endcase
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end
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endmodule
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@ -0,0 +1,80 @@
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module FSM_minute(
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input wire rst,
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input wire clk,
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input wire [5:0] min_in,
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input wire min_in_load,
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input wire [5:0] sec_count,
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output reg [5:0] min_out);
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reg [2:0] ps, ns;
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wire [5:0] min_data_add;
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reg [5:0] min_data;
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reg [5:0] min_ps, min_ns;
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reg [1:0] min_sel;
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wire min_count;
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always@(posedge clk)
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begin
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if(rst) ps <= 3'd0;
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else ps <= ns;
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end
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always@(posedge clk)
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begin
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if(rst) min_ps <= 6'd0;
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else min_ps <= min_ns;
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end
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always@(*)
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begin
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min_sel = 2'd0;
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case(ps)
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3'd0: begin
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ns = 3'd1;
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end
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3'd1: begin
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if(min_in_load) begin
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min_sel = 2'd1;
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min_out = min_data;
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ns = 3'd2;
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min_ns = min_data;
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end
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else ns = 3'd1;
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end
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3'd2: begin
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if(min_count == 1'd1) begin
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if(min_data == 6'd59) begin
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min_out = min_data;
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ns = 3'd2;
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min_ns = 6'd0;
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end
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else begin
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min_out = min_data;
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ns = 3'd2;
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min_ns = min_data_add;
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end
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end
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else begin
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min_out = min_data;
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min_ns = min_data;
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ns = 3'd2;
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end
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end
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default: begin
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ns = 3'd0;
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end
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endcase
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end
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assign min_data_add = min_data + 1;
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assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0;
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always@(*)
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begin
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case(min_sel)
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2'd0: min_data = min_ps;
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2'd1: min_data = min_in;
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endcase
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end
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endmodule
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@ -0,0 +1,70 @@
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module FSM_second(
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input wire rst,
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input wire clk,
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input wire [5:0] sec_in,
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input wire sec_in_load,
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output reg [5:0] sec_out);
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reg [2:0] ps, ns;
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wire [5:0] sec_data_add;
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reg [5:0] sec_data;
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reg [5:0] sec_ps, sec_ns;
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reg [1:0] sec_sel;
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always@(posedge clk)
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begin
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if(rst) ps <= 3'd0;
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else ps <= ns;
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end
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always@(posedge clk)
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begin
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if(rst) sec_ps <= 6'd0;
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else sec_ps <= sec_ns;
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end
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always@(*)
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begin
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sec_sel = 2'd0;
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case(ps)
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3'd0: begin
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ns = 3'd1;
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end
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3'd1: begin
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if(sec_in_load) begin
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sec_sel = 2'd1;
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sec_out = sec_data;
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ns = 3'd2;
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sec_ns = sec_data_add;
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end
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else ns = 3'd1;
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end
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3'd2: begin
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if(sec_data == 6'd59) begin
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sec_out = sec_data;
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ns = 3'd2;
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sec_ns = 6'd0;
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end
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else begin
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sec_out = sec_data;
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ns = 3'd2;
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sec_ns = sec_data_add;
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end
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end
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default: begin
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ns = 3'd0;
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end
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endcase
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end
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assign sec_data_add = sec_data + 1;
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always@(*)
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begin
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case(sec_sel)
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2'd0: sec_data = sec_ps;
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2'd1: sec_data = sec_in;
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endcase
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end
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endmodule
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@ -0,0 +1,34 @@
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module FSM_three_tb;
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reg rst;
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reg clk;
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reg [5:0] sec_in, min_in, hour_in;
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reg load_in;
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wire [5:0] sec_out, min_out, hour_out;
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FSM_top FSM_1(
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.rst(rst),
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.clk(clk),
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.sec_in(sec_in),
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.load_in(load_in),
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.sec_out(sec_out),
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.min_in(min_in),
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.min_out(min_out),
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.hour_in(hour_in),
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.hour_out(hour_out));
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initial begin
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#0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5;
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#100 rst = 1'd0;
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#50 load_in = 1'd0;
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end
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always begin
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#10 clk = ~clk;
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end
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initial begin
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#100000 $stop;
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end
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endmodule
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@ -0,0 +1,37 @@
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module FSM_top(
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input wire rst,
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input wire clk,
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input wire load_in,
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input wire [5:0] sec_in,
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input wire [5:0] min_in,
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input wire [5:0] hour_in,
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output wire [5:0] sec_out,
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output wire [5:0] min_out,
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output wire [5:0] hour_out
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);
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FSM_second FSM_sec(
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.rst(rst),
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.clk(clk),
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.sec_in(sec_in),
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.sec_in_load(load_in),
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.sec_out(sec_out));
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FSM_minute FSM_min(
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.rst(rst),
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.clk(clk),
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.min_in(min_in),
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.min_in_load(load_in),
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.sec_count(sec_out),
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.min_out(min_out));
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FSM_hour FSM_hr(
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.rst(rst),
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.clk(clk),
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.hour_in(hour_in),
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.hour_in_load(load_in),
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.min_count(min_out),
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.hour_out(hour_out),
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.sec_count(sec_out));
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endmodule
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@ -0,0 +1,27 @@
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module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
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output zero_flag_out;
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output reg [7:0]alu_out;
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input [7:0]Reg_Y_in,Bus_1_in;
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input [7:0]IR_code;
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wire [3:0]opcode=IR_code[7:4];
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always@(*)
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begin
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case(opcode)
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1: alu_out=Reg_Y_in+Bus_1_in;
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2: alu_out=Bus_1_in+~(Reg_Y_in)+1;
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3: alu_out=Reg_Y_in&(Bus_1_in);
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4: alu_out=~(Bus_1_in);
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default:alu_out=8'b0;
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endcase
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end
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assign zero_flag_out=~|alu_out;
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endmodule
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@ -0,0 +1,211 @@
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module Controller(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
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Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,write,
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zero,instruction,nclk,rst);
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//狀態
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parameter S_idle=0,S_fet1=1,S_fet2=2,S_dec=3,
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S_ex1=4,S_rd1=5,S_rd2=6,S_wr1=7,S_wr2=8,
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S_br1=9,S_br2=10,S_halt=11;
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//指令
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parameter NOP=0,ADD=1,SUB=2,AND=3,NOT=4,
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RD=5,WR=6,BR=7,BRZ=8;
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output reg L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
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L_IR,L_ADD_R,L_R_Y,L_R_Z,write;
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output reg[2:0]Sel_Bus1;
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output reg [1:0]Sel_Bus2;
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input zero,nclk,rst;
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input [7:0]instruction;
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reg [15:0]Con_out;
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reg [3:0]PS,NS;
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reg err_flag;
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wire [1:0]src=instruction[3:2];
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wire [1:0]dest=instruction[1:0];
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wire [3:0]opcode=instruction[7:4];
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always@(posedge nclk)
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begin
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if(rst==1)PS<=0;
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else PS<=NS;
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end
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always@(PS,opcode,src,dest,zero)
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begin
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L_R0=0;
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L_R1=0;
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L_R2=0;
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L_R3=0;
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L_PC=0;
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Inc_PC=0;
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Sel_Bus1=0;
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L_IR=0;
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L_ADD_R=0;
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L_R_Y=0;
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L_R_Z=0;
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Sel_Bus2=0;
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write=0;
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err_flag=0;
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case(PS)
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S_idle: NS=S_fet1;
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S_fet1: begin
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NS=S_fet2;
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Sel_Bus1=3'b100;//Sel_PC
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Sel_Bus2=2'b01;//Sel_Bus1
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L_ADD_R=1;
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end
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S_fet2: begin
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NS=S_dec;
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Sel_Bus2=2'b10;//Sel_Mem
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L_IR=1;
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Inc_PC=1;
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end
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S_dec: begin
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case(opcode)
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NOP:NS=S_fet1;
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ADD,SUB,AND:begin
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NS=S_ex1;
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Sel_Bus2=2'b01;//Sel_Bus1
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L_R_Y=1;
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case(src)
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0: Sel_Bus1=3'b000;//R0
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1: Sel_Bus1=3'b001;//R1
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2: Sel_Bus1=3'b010;//R2
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3: Sel_Bus1=3'b011;//R3
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default err_flag=1;
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endcase
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end//ADD,SUB,AND
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NOT:begin
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NS=S_fet1;
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L_R_Z=1;
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Sel_Bus2=2'b00;//Sel_ALU
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case(src)
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0: Sel_Bus1=3'b000;//R0
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1: Sel_Bus1=3'b001;//R1
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2: Sel_Bus1=3'b010;//R2
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3: Sel_Bus1=3'b011;//R3
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default err_flag=1;
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endcase
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case(dest)
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0: L_R0=1;
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1: L_R1=1;
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2: L_R2=1;
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3: L_R3=1;
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default err_flag=1;
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endcase
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end//NOT
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RD: begin
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NS=S_rd1;
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Sel_Bus1=3'b100;//Sel_PC
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Sel_Bus2=3'b001;//Sel_Bus1
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L_ADD_R=1;
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end//RD
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WR: begin
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NS=S_wr1;
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Sel_Bus1=3'b100;//Sel_PC
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Sel_Bus2=3'b001;//Sel_Bus1
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L_ADD_R=1;
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end//WR
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BR: begin
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NS=S_br1;
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Sel_Bus1=3'b100;//Sel_PC
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Sel_Bus2=3'b001;//Sel_Bus1
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L_ADD_R=1;
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end//BR
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BRZ:begin
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if(zero==1)begin
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NS=S_br1;
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Sel_Bus1=3'b100;//Sel_PC
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Sel_Bus2=3'b001;//Sel_Bus1
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L_ADD_R=1;
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end
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else begin
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NS=S_fet1;
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Inc_PC=1;
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end
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end//BRZ
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default NS=S_halt;
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endcase//opcode
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end
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S_ex1: begin
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NS=S_fet1;
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L_R_Z=1;
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Sel_Bus2=2'b00;//Sel_ALU
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case(dest)
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0: begin Sel_Bus1=3'b000;L_R0=1;end
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1: begin Sel_Bus1=3'b001;L_R1=1;end
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2: begin Sel_Bus1=3'b010;L_R2=1;end
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3: begin Sel_Bus1=3'b011;L_R3=1;end
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default err_flag=1;
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endcase
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end
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S_rd1: begin
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NS=S_rd2;
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Inc_PC=1;
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Sel_Bus2=2'b10;//Sel_Mem
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L_ADD_R=1;
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end
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S_wr1: begin
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NS=S_wr2;
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Inc_PC=1;
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Sel_Bus2=2'b10;//Sel_Mem
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L_ADD_R=1;
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end
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S_rd2: begin
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NS=S_fet1;
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Sel_Bus2=2'b10;//Sel_Mem
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case(dest)
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0: L_R0=1;
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1: L_R1=1;
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2: L_R2=1;
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3: L_R3=1;
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default err_flag=1;
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endcase
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end
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S_wr2: begin
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NS=S_fet1;
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write=1;
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case(src)
|
||||
0: Sel_Bus1=3'b000;//R0
|
||||
1: Sel_Bus1=3'b001;//R1
|
||||
2: Sel_Bus1=3'b010;//R2
|
||||
3: Sel_Bus1=3'b011;//R3
|
||||
default err_flag=1;
|
||||
endcase
|
||||
end
|
||||
|
||||
S_br1: begin
|
||||
NS=S_br2;
|
||||
Sel_Bus2=2'b10;//Sel_Mem
|
||||
L_ADD_R=1;
|
||||
end
|
||||
|
||||
S_br2: begin
|
||||
NS=S_fet1;
|
||||
Sel_Bus2=2'b10;//Sel_Mem
|
||||
L_PC=1;
|
||||
end
|
||||
S_halt: NS=S_halt;
|
||||
default NS=S_idle;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
module IR(IR_out,IR_in,load,clk,rst);
|
||||
|
||||
output reg [7:0]IR_out;
|
||||
input [7:0]IR_in;
|
||||
input load,clk,rst;
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(rst==1)IR_out<=8'b0;
|
||||
else if(load==1)IR_out<=IR_in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
module Memory(Data_out,Address);
|
||||
|
||||
output [7:0]Data_out;
|
||||
input [7:0]Address;
|
||||
|
||||
reg [7:0]mem[255:0];
|
||||
assign Data_out=mem[Address];
|
||||
|
||||
always@(Address)
|
||||
begin
|
||||
case(Address)
|
||||
//opcode_src_dest
|
||||
//NOP
|
||||
0: mem[Address]=8'b0000_00_00;
|
||||
|
||||
//rd 00 10 //Read MEM[130] to R2
|
||||
1: mem[Address]=8'b0101_00_10; //Instruction
|
||||
2: mem[Address]=130; //Address
|
||||
|
||||
//rd 00 11 //Read MEM[131] to R3
|
||||
3: mem[Address]=8'b0101_00_11; //Instruction
|
||||
4: mem[Address]=131; //Address
|
||||
|
||||
//rd 00 01 //Read MEM[128] to R1
|
||||
5: mem[Address]=8'b0101_00_01; //Instruction
|
||||
6: mem[Address]=128; //Address
|
||||
|
||||
//rd 00 00 //Read MEM[129] to R0
|
||||
7: mem[Address]=8'b0101_00_00; //Instruction
|
||||
8: mem[Address]=129; //Address
|
||||
|
||||
//Sub 00 01 //Sub R1-R0 to R1
|
||||
9: mem[Address]=8'b0010_00_01; //Instruction
|
||||
|
||||
//BRZ 00 00
|
||||
10: mem[Address]=8'b1000_00_00; //Instruction
|
||||
11: mem[Address]=134; //Address
|
||||
|
||||
//Add 10 11 //Add R2+R3 to R3
|
||||
12: mem[Address]=8'b00011011;
|
||||
|
||||
//BR
|
||||
13: mem[Address]=8'b01110011; //Instruction
|
||||
14: mem[Address]=140; //Address
|
||||
|
||||
128:mem[Address]=6;
|
||||
129:mem[Address]=1;
|
||||
130:mem[Address]=2;
|
||||
131:mem[Address]=0;
|
||||
134:mem[Address]=139; //Address
|
||||
135:mem[Address]=0;
|
||||
//HAL
|
||||
139:mem[Address]=8'b1111_00_00; //Instruction
|
||||
140:mem[Address]=9; //Address
|
||||
default mem[Address]=8'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
module Mux_31(Y,A0,A1,A2,sel);
|
||||
|
||||
output [7:0]Y;
|
||||
input [7:0]A2,A1,A0;
|
||||
input [1:0]sel;
|
||||
|
||||
reg [7:0]Y;
|
||||
|
||||
always@(*)
|
||||
begin
|
||||
case(sel)
|
||||
0: Y=A0;
|
||||
1: Y=A1;
|
||||
2: Y=A2;
|
||||
default:Y=8'bz;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
module Mux_51(Y,A0,A1,A2,A3,A4,sel);
|
||||
|
||||
output [7:0]Y;
|
||||
input [7:0]A4,A3,A2,A1,A0;
|
||||
input [2:0]sel;
|
||||
|
||||
reg [7:0]Y;
|
||||
|
||||
always@(*)
|
||||
begin
|
||||
case(sel)
|
||||
0: Y=A0;
|
||||
1: Y=A1;
|
||||
2: Y=A2;
|
||||
3: Y=A3;
|
||||
4: Y=A4;
|
||||
default:Y=8'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
module PC(PC_out,PC_in,load,inc,clk,rst);
|
||||
|
||||
output [7:0]PC_out;
|
||||
input [7:0]PC_in;
|
||||
input load,inc,clk,rst;
|
||||
|
||||
reg [7:0]PC_out;
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(rst==1)PC_out<=8'b0;
|
||||
else if(load==1)PC_out<=PC_in;
|
||||
else if(inc==1)PC_out<=PC_out+8'b00000001;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
|
||||
|
||||
output [7:0]bus_1_out;
|
||||
input clk,rst;
|
||||
output [7:0]Reg_R0_out;
|
||||
output [7:0]Reg_R1_out;
|
||||
output [7:0]Reg_R2_out;
|
||||
output [7:0]Reg_R3_out;
|
||||
|
||||
wire [7:0]bus_1_out,MEMAddress;
|
||||
wire clk,rst;
|
||||
wire [7:0]MEMdataout;
|
||||
wire [7:0]Reg_R0_out;
|
||||
wire [7:0]Reg_R1_out;
|
||||
wire [7:0]Reg_R2_out;
|
||||
wire [7:0]Reg_R3_out;
|
||||
|
||||
|
||||
RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
|
||||
|
||||
Memory MEM(MEMdataout,MEMAddress);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
|
||||
|
||||
output [7:0]bus_1_out,MEMAddress;
|
||||
input clk,rst;
|
||||
input [7:0]MEMdataout;
|
||||
output [7:0]Reg_R0_out;
|
||||
output [7:0]Reg_R1_out;
|
||||
output [7:0]Reg_R2_out;
|
||||
output [7:0]Reg_R3_out;
|
||||
|
||||
wire [7:0]BUS_2,BUS_1,MEMAddress;
|
||||
wire [7:0]alu_out;
|
||||
wire [7:0]MEMdataout;
|
||||
wire [7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out;
|
||||
wire [7:0]IR_out;
|
||||
wire zero_flag_out;
|
||||
wire [2:0]Sel_Bus1;
|
||||
wire [1:0]Sel_Bus2;
|
||||
wire L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero;
|
||||
|
||||
assign bus_1_out=BUS_1;
|
||||
assign bus_2_out=BUS_2;
|
||||
|
||||
Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst);
|
||||
//module PC(PC_out,PC_in,load,inc,clk,rst);
|
||||
PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst);
|
||||
//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
|
||||
ALU Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out);
|
||||
//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite);
|
||||
//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite);
|
||||
//module Mux_31(Y,A0,A1,A2,sel);
|
||||
Mux_31 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2);
|
||||
//module Reg_1bit(Q,D,load,clk,rst);
|
||||
Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst);
|
||||
//module Reg_8bit(Q,D,load,clk,rst);
|
||||
Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst);
|
||||
Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst);
|
||||
//R0~R3
|
||||
Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst);
|
||||
Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst);
|
||||
Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst);
|
||||
Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst);
|
||||
//module Mux_51(Y,A0,A1,A2,A3,A4,sel);
|
||||
Mux_51 Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1);
|
||||
//module IR(IR_out,IR_in,load,clk,rst);
|
||||
IR Instruction_Register(IR_out,BUS_2,L_IR,clk,rst);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
`timescale 1ns/1ns
|
||||
|
||||
module RISC_testbench;
|
||||
|
||||
wire [7:0]bus_1_out;
|
||||
reg clk,rst;
|
||||
wire [7:0]Reg_R0_out;
|
||||
wire [7:0]Reg_R1_out;
|
||||
wire [7:0]Reg_R2_out;
|
||||
wire [7:0]Reg_R3_out;
|
||||
|
||||
/* wire [7:0]MEMAddress;
|
||||
wire [7:0]MEMdataout;
|
||||
wire MEMwrite; */
|
||||
|
||||
/* assign MEMAddress = top.MEMAddress;
|
||||
assign MEMdataout = top.MEMdataout;
|
||||
assign MEMwrite = top.MEMwrite; */
|
||||
|
||||
RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
|
||||
|
||||
always#20 clk=~clk;
|
||||
|
||||
initial
|
||||
begin
|
||||
clk=0;rst=1;
|
||||
#30 rst=0;
|
||||
#6000 $stop;
|
||||
end
|
||||
|
||||
/* //----------
|
||||
|
||||
integer fp;
|
||||
initial
|
||||
begin
|
||||
fp = $fopen("RISC_xa.vec");
|
||||
|
||||
$fdisplay(fp, "radix 1 1 44 44 44 44 44 1 44 44");
|
||||
$fdisplay(fp, "vname clk rst Reg_R0_out[[7:0]] Reg_R1_out[[7:0]] Reg_R2_out[[7:0]] Reg_R3_out[[7:0]] bus_1_out[[7:0]] MEMwrite MEMAddress MEMdataout");
|
||||
$fdisplay(fp, " io i i oo oo oo oo oo o oo ii");
|
||||
$fdisplay(fp, "slope 0.3");
|
||||
$fdisplay(fp, " vih 3.3");
|
||||
$fdisplay(fp, " vil 0");
|
||||
$fdisplay(fp, "tunit ns");
|
||||
end
|
||||
always@(clk)
|
||||
begin
|
||||
$fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout);
|
||||
end
|
||||
|
||||
//---------- */
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
module Reg_1bit(Q,D,load,clk,rst);
|
||||
|
||||
output Q;
|
||||
input D;
|
||||
input load,clk,rst;
|
||||
|
||||
reg Q;
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(rst==1)Q<=0;
|
||||
else if(load==1)Q<=D;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
module Reg_8bit(Q,D,load,clk,rst);
|
||||
|
||||
output [7:0]Q;
|
||||
input [7:0]D;
|
||||
input load,clk,rst;
|
||||
|
||||
reg [7:0]Q;
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(rst==1)Q<=8'b0;
|
||||
else if(load==1)Q<=D;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
module ACC(
|
||||
output [7:0] acc_out1,
|
||||
output [7:0] acc_out2,
|
||||
input [7:0] acc_in,
|
||||
input la_,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
reg [7:0] q;
|
||||
|
||||
always @(posedge clk)
|
||||
if (~clr_) q <= 8'b0;
|
||||
else if(~la_) q <= acc_in;
|
||||
|
||||
assign acc_out1 = q;
|
||||
assign acc_out2 = q;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
module ADDSUB(
|
||||
output [7:0] ADDSUB_out,
|
||||
input [7:0] ADDSUB_in1,
|
||||
input [7:0] ADDSUB_in2,
|
||||
input su
|
||||
);
|
||||
|
||||
wire [7:0] d;
|
||||
|
||||
assign d = su ? ADDSUB_in1 - ADDSUB_in2 : ADDSUB_in1 + ADDSUB_in2;
|
||||
assign ADDSUB_out = d;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
module BRegister(
|
||||
output reg [7:0] BRegister_out,
|
||||
input [7:0] BRegister_in,
|
||||
input lb_,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
always @(posedge clk)
|
||||
if(~clr_) BRegister_out <= 8'b0;
|
||||
else if(~lb_) BRegister_out <= BRegister_in;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
module Controller(
|
||||
output reg [11:0] control_signals,
|
||||
input [3:0] opcode,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
reg [3:0] ps, ns;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(~clr_) ps <= 4'd0;
|
||||
else ps <= ns;
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
case(ps)
|
||||
0:
|
||||
begin
|
||||
control_signals = 12'h3e3;
|
||||
ns = 4'd1;
|
||||
end
|
||||
|
||||
1: //T1
|
||||
begin
|
||||
control_signals = 12'h5e3;
|
||||
ns = 4'd2;
|
||||
end
|
||||
|
||||
2: //T2
|
||||
begin
|
||||
// control_signals = 12'hbe3;
|
||||
control_signals = 12'h863;
|
||||
ns = 4'd3;
|
||||
end
|
||||
|
||||
3: //T3
|
||||
begin
|
||||
// control_signals = 12'h263;
|
||||
control_signals = 12'h3e3;
|
||||
if(opcode == 4'd0) //LDA
|
||||
ns = 4'd4;
|
||||
else if(opcode == 4'd1) //ADD
|
||||
ns = 4'd6;
|
||||
else if(opcode == 4'd2) //SUB
|
||||
ns = 4'd9;
|
||||
else if(opcode == 4'd14) //OUT
|
||||
ns = 4'd12;
|
||||
else if(opcode == 4'd15) //HLT
|
||||
ns = 4'd13;
|
||||
end
|
||||
|
||||
4: //LDA
|
||||
begin
|
||||
control_signals = 12'h1a3;
|
||||
ns = 4'd5;
|
||||
end
|
||||
|
||||
5: //LDA
|
||||
begin
|
||||
control_signals = 12'h2c3;
|
||||
ns = 4'd1;
|
||||
end
|
||||
|
||||
6: //ADD
|
||||
begin
|
||||
control_signals = 12'h1a3;
|
||||
ns = 4'd7;
|
||||
end
|
||||
|
||||
7: //ADD
|
||||
begin
|
||||
control_signals = 12'h2e1;
|
||||
ns = 4'd8;
|
||||
end
|
||||
|
||||
8: //ADD
|
||||
begin
|
||||
control_signals = 12'h3c7;
|
||||
ns = 4'd1;
|
||||
end
|
||||
|
||||
9: //SUB
|
||||
begin
|
||||
control_signals = 12'h1a3;
|
||||
ns = 4'd10;
|
||||
end
|
||||
|
||||
10: //SUB
|
||||
begin
|
||||
control_signals = 12'h2e1;
|
||||
ns = 4'd11;
|
||||
end
|
||||
|
||||
11: //SUB
|
||||
begin
|
||||
control_signals = 12'h3cf;
|
||||
ns = 4'd1;
|
||||
end
|
||||
|
||||
12: //OUT
|
||||
begin
|
||||
control_signals = 12'h3f2;
|
||||
ns = 4'd1;
|
||||
end
|
||||
|
||||
13: //HLT
|
||||
ns = 4'd13;
|
||||
|
||||
default:
|
||||
begin
|
||||
ns = 4'd0;
|
||||
control_signals = 12'h3e3;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module IR(
|
||||
output [7:4] opcode,
|
||||
output [3:0] oprand,
|
||||
input wire [7:0] IR_in,
|
||||
input li_,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
reg [7:0] q;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(~clr_) q <=8'b0;
|
||||
else if(~li_) q <= IR_in;
|
||||
end
|
||||
|
||||
assign opcode = q[7:4];
|
||||
assign oprand = q[3:0];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
module MAR(
|
||||
output reg [3:0] mar_out,
|
||||
input wire [3:0] mar_in,
|
||||
input lm_,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
always @(posedge clk)
|
||||
if(~clr_) mar_out <= 4'b0;
|
||||
else if(~lm_) mar_out <= mar_in;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
module OutputRegister(
|
||||
output reg [7:0] OutputRegister_out,
|
||||
input [7:0] OutputRegister_in,
|
||||
input lo_,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
always @(posedge clk)
|
||||
if(~clr_) OutputRegister_out <= 8'b0;
|
||||
else if(~lo_) OutputRegister_out <= OutputRegister_in;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
module PC(
|
||||
output reg [3:0] pc_out,
|
||||
input cp,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(~clr_) pc_out <= 0;
|
||||
else if (cp) pc_out <= pc_out + 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
module ROM(
|
||||
output reg [7:0] rom_out,
|
||||
input [3:0] rom_in
|
||||
);
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
rom_out = 8'bx;
|
||||
case(rom_in)
|
||||
4'b0000: rom_out = 8'b0000_1001; //LDA
|
||||
4'b0001: rom_out = 8'b0001_1010; //ADD
|
||||
4'b0010: rom_out = 8'b0001_1011; //ADD
|
||||
4'b0011: rom_out = 8'b0010_1100; //SUB
|
||||
4'b0100: rom_out = 8'b1110_xxxx; //OUT
|
||||
4'b0101: rom_out = 8'b1111_xxxx; //HLT
|
||||
4'b0110: rom_out = 8'bxxxx_xxxx;
|
||||
4'b0111: rom_out = 8'bxxxx_xxxx;
|
||||
4'b1000: rom_out = 8'bxxxx_xxxx;
|
||||
4'b1001: rom_out = 8'b0001_0000;
|
||||
4'b1010: rom_out = 8'b0001_0100;
|
||||
4'b1011: rom_out = 8'b0001_1000;
|
||||
4'b1100: rom_out = 8'b0010_0000;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
module SAPone(
|
||||
output wire [7:0] SAP_out,
|
||||
output wire [11:0] con,
|
||||
output reg [7:0] bus,
|
||||
input clk,
|
||||
input clr_
|
||||
);
|
||||
|
||||
wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_;
|
||||
wire [7:0] acc_out2, BRegister_out, OutputRegister_out;
|
||||
wire [3:0] IR_out, mar_out;
|
||||
wire [4:0] bus_sel;
|
||||
wire [3:0] pc_out, oprand;
|
||||
wire [7:0] rom_out, acc_out1, ADDSUB_out;
|
||||
|
||||
assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con;
|
||||
assign bus_sel = {ep, ce_, ei_, ea, eu};
|
||||
|
||||
always@(*)
|
||||
begin
|
||||
case(bus_sel)
|
||||
5'b11100: bus[3:0] = pc_out;
|
||||
5'b00100: bus[7:0] = rom_out;
|
||||
5'b01000: bus[3:0] = oprand;
|
||||
5'b01110: bus[7:0] = acc_out1;
|
||||
5'b01101: bus[7:0] = ADDSUB_out;
|
||||
default: bus[7:0] = 8'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
PC pc1(
|
||||
.pc_out(pc_out),
|
||||
.cp(cp),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
MAR mar1(
|
||||
.mar_out(mar_out),
|
||||
.mar_in(bus[3:0]),
|
||||
.lm_(lm_),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
ROM roml(
|
||||
.rom_out(rom_out),
|
||||
.rom_in(mar_out)
|
||||
);
|
||||
|
||||
IR ir1(
|
||||
.opcode(IR_out),
|
||||
.oprand(oprand),
|
||||
.IR_in(bus[7:0]),
|
||||
.li_(li_),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
Controller cont1(
|
||||
.control_signals(con),
|
||||
.opcode(IR_out),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
ACC acc1(
|
||||
.acc_out1(acc_out1),
|
||||
.acc_out2(acc_out2),
|
||||
.acc_in(bus[7:0]),
|
||||
.la_(la_),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
ADDSUB addsub1(
|
||||
.ADDSUB_out(ADDSUB_out),
|
||||
.ADDSUB_in1(acc_out2),
|
||||
.ADDSUB_in2(BRegister_out),
|
||||
.su(su)
|
||||
);
|
||||
|
||||
BRegister bregister1(
|
||||
.BRegister_out(BRegister_out),
|
||||
.BRegister_in(bus[7:0]),
|
||||
.lb_(lb_),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
OutputRegister outputregister1(
|
||||
.OutputRegister_out(SAP_out),
|
||||
.OutputRegister_in(bus[7:0]),
|
||||
.lo_(lo_),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
module testSAPone;
|
||||
|
||||
wire [7:0] SAP_out;
|
||||
wire [11:0] con;
|
||||
wire [7:0] bus;
|
||||
// wire clk_out, clr_out;
|
||||
reg clk, clr_;
|
||||
|
||||
always #5 clk = ~clk;
|
||||
|
||||
SAPone sapone1(
|
||||
.SAP_out(SAP_out),
|
||||
.con(con),
|
||||
.bus(bus),
|
||||
// .clk_out(clk_out),
|
||||
// .clr_out(clr_out),
|
||||
.clk(clk),
|
||||
.clr_(clr_)
|
||||
);
|
||||
|
||||
// PC pc1(bus[3:0], clk, clr_, cp, ep);
|
||||
// MAR mar1(mar, clk, lm_, bus[3:0]);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 0; clr_ = 0;
|
||||
#10 clr_ = 1;
|
||||
|
||||
|
||||
|
||||
#990 $stop;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
module counter_original(clk_counter, q_counter, rst_counter);
|
||||
|
||||
input clk_counter;
|
||||
input rst_counter;
|
||||
output [7:0] q_counter;
|
||||
reg [7:0] q_counter;
|
||||
|
||||
always @ (posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter)
|
||||
q_counter <= 8'b00000000;
|
||||
else
|
||||
q_counter <= q_counter + 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
|
||||
|
||||
module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
|
||||
wire _00_;
|
||||
wire _01_;
|
||||
input clk_counter;
|
||||
wire n22;
|
||||
wire n26;
|
||||
wire n30;
|
||||
wire n34;
|
||||
wire n38;
|
||||
wire n42;
|
||||
wire n46;
|
||||
wire n50;
|
||||
output \q_counter[0] ;
|
||||
reg \q_counter[0] ;
|
||||
output \q_counter[1] ;
|
||||
reg \q_counter[1] ;
|
||||
output \q_counter[2] ;
|
||||
reg \q_counter[2] ;
|
||||
output \q_counter[3] ;
|
||||
reg \q_counter[3] ;
|
||||
output \q_counter[4] ;
|
||||
reg \q_counter[4] ;
|
||||
output \q_counter[5] ;
|
||||
reg \q_counter[5] ;
|
||||
output \q_counter[6] ;
|
||||
reg \q_counter[6] ;
|
||||
output \q_counter[7] ;
|
||||
reg \q_counter[7] ;
|
||||
input rst_counter;
|
||||
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[0] <= 1'b0;
|
||||
else \q_counter[0] <= n22;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[1] <= 1'b0;
|
||||
else \q_counter[1] <= n26;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[2] <= 1'b0;
|
||||
else \q_counter[2] <= n30;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[3] <= 1'b0;
|
||||
else \q_counter[3] <= n34;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[4] <= 1'b0;
|
||||
else \q_counter[4] <= n38;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[5] <= 1'b0;
|
||||
else \q_counter[5] <= n42;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[6] <= 1'b0;
|
||||
else \q_counter[6] <= n46;
|
||||
end
|
||||
always @(posedge clk_counter)
|
||||
begin
|
||||
if(rst_counter) \q_counter[7] <= 1'b0;
|
||||
else \q_counter[7] <= n50;
|
||||
end
|
||||
|
||||
assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
|
||||
assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] };
|
||||
assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] };
|
||||
assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] };
|
||||
assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
|
||||
assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] };
|
||||
assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
|
||||
assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] };
|
||||
assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] };
|
||||
assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
|
||||
endmodule
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os)
|
||||
|
||||
.model counter
|
||||
.inputs clk_counter rst_counter
|
||||
.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7]
|
||||
.names $false
|
||||
.names $true
|
||||
1
|
||||
.names $undef
|
||||
.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0]
|
||||
0011 1
|
||||
1000 1
|
||||
1001 1
|
||||
1010 1
|
||||
.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_
|
||||
111111 1
|
||||
.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0]
|
||||
010 1
|
||||
100 1
|
||||
.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0]
|
||||
010 1
|
||||
100 1
|
||||
.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_
|
||||
11111 1
|
||||
.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0]
|
||||
0011 1
|
||||
1000 1
|
||||
1001 1
|
||||
1010 1
|
||||
.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0]
|
||||
001111 1
|
||||
100000 1
|
||||
100001 1
|
||||
100010 1
|
||||
100011 1
|
||||
100100 1
|
||||
100101 1
|
||||
100110 1
|
||||
100111 1
|
||||
101000 1
|
||||
101001 1
|
||||
101010 1
|
||||
101011 1
|
||||
101100 1
|
||||
101101 1
|
||||
101110 1
|
||||
.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0]
|
||||
00111 1
|
||||
10000 1
|
||||
10001 1
|
||||
10010 1
|
||||
10011 1
|
||||
10100 1
|
||||
10101 1
|
||||
10110 1
|
||||
.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0]
|
||||
010 1
|
||||
100 1
|
||||
.names q_counter[0] rst_counter $0\q_counter[0][0:0]
|
||||
00 1
|
||||
.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2
|
||||
.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2
|
||||
.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2
|
||||
.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2
|
||||
.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2
|
||||
.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2
|
||||
.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2
|
||||
.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2
|
||||
.end
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
clk_counter 0.500000 2.000000
|
||||
rst_counter 0.492200 0.201800
|
||||
q_counter[0] 0.281800 0.563400
|
||||
q_counter[1] 0.248200 0.273600
|
||||
q_counter[2] 0.183200 0.125600
|
||||
q_counter[3] 0.097400 0.044800
|
||||
q_counter[4] 0.022600 0.007200
|
||||
q_counter[5] 0.002200 0.000800
|
||||
q_counter[6] 0.000000 0.000000
|
||||
q_counter[7] 0.000000 0.000000
|
||||
$0\q_counter[7][0:0] 0 0
|
||||
$0\q_counter[6][0:0] 0 0
|
||||
$0\q_counter[5][0:0] 0 0
|
||||
$0\q_counter[4][0:0] 0 0
|
||||
$0\q_counter[3][0:0] 0 0
|
||||
$0\q_counter[2][0:0] 0 0
|
||||
$0\q_counter[1][0:0] 0 0
|
||||
$0\q_counter[0][0:0] 0 0
|
||||
$abc$3686$new_n23_ 0 0
|
||||
$abc$3686$new_n20_ 0 0
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
module counter_tb;
|
||||
|
||||
reg clk_counter, rst_counter;
|
||||
wire [7:0] q_counter;
|
||||
|
||||
counter_original C_1(
|
||||
clk_counter,
|
||||
q_counter,
|
||||
rst_counter);
|
||||
|
||||
initial begin
|
||||
#0 rst_counter = 1'b1; clk_counter = 1'b0;
|
||||
#100 rst_counter = 1'b0;
|
||||
end
|
||||
|
||||
always begin
|
||||
#10 clk_counter = ~clk_counter;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5000 $stop;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue