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[Arch] Bug fix in architecture. Now soft adder modes are accepted

This commit is contained in:
tangxifan 2021-02-01 13:43:39 -07:00
parent d8927e12e8
commit 10302752a7
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -488,7 +488,7 @@
</mode>
<!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Arithmetic mode definition begin -->
<mode name="arithematic">
<mode name="arithmetic">
<pb_type name="soft_adder" num_pb="1">
<input name="in" num_pins="4"/>
<input name="cin" num_pins="1"/>
@ -523,7 +523,7 @@
<direct name="direct5" input="adder_lut4.lut2_out[1:1]" output="carry_follower.a"/>
<direct name="direct6" input="adder_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
<direct name="direct7" input="carry_follower.cout" output="soft_adder.cout"/>
<direct name="direct8" input="adder_lut4.lut4_out[0:0]" output="ff[0:0].D">
<direct name="direct8" input="adder_lut4.lut4_out[0:0]" output="ff[0:0].D"/>
<complete name="complete1" input="soft_adder.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="adder_lut4.lut4_out[0:0] ff[0:0].Q" output="soft_adder.out[0:0]">
<delay_constant max="25e-12" in_port="adder_lut4.lut4_out[0:0]" out_port="soft_adder.out[0:0]"/>