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[Architecture] Bug fix for architecture using set only

This commit is contained in:
tangxifan 2020-09-23 22:04:24 -06:00
parent 46b12611a9
commit 77a1f99564
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml
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@ -146,7 +146,7 @@
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch_set_set" prefix="config_latch_set_set" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_set_set.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_set_set.v">
<circuit_model type="sram" name="config_latch_set" prefix="config_latch_set" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_set.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_set.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>