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Removing 2 more tests which are variant of and design

This commit is contained in:
Lalit Sharma 2021-02-19 09:11:19 -08:00
parent d4c5a5655a
commit 576e6753f6
5 changed files with 4 additions and 72 deletions
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6
openfpga_flow/benchmarks/quicklogic_tests/and2_latch/and2_latch.act
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@ -1,6 +0,0 @@
a 0.492800 0.201000
b 0.502000 0.197200
clk 0.500000 2.000000
d 0.240200 0.171200
c 0.240200 0.044100
n1 0.240200 0.044100

29
openfpga_flow/benchmarks/quicklogic_tests/and2_latch/and2_latch.v
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@ -1,29 +0,0 @@
/////////////////////////////////////////
// Functionality: 2-input AND with clocked
// and combinational outputs
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2_latch(
a,
b,
clk,
c,
d);
input wire clk;
input wire a;
input wire b;
output wire c;
output reg d;
assign c = a & b;
always @(posedge clk) begin
d <= c;
end
endmodule

4
openfpga_flow/benchmarks/quicklogic_tests/and2_or2/and2_or2.act
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@ -1,4 +0,0 @@
a 0.5 0.5
b 0.5 0.5
c 0.25 0.25
d 0.25 0.25

22
openfpga_flow/benchmarks/quicklogic_tests/and2_or2/and2_or2.v
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@ -1,22 +0,0 @@
/////////////////////////////////////////
// Functionality: 2-input AND + 2-input OR
// This benchmark is designed to test fracturable LUTs
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2_or2(
a,
b,
c,
d);
input wire a;
input wire b;
output wire c;
output wire d;
assign c = a & b;
assign d = a | b;
endmodule

15
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
View File

@ -25,14 +25,13 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/and2_latch/and2_latch.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.v
# RS decoder needs 1.5k LUT4, exceeding device capacity
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/and2_or2/and2_or2.v
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
# counter120bitx5 requires 5 clocks
@ -47,13 +46,11 @@ bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
# sdc_controller requires 4 clocks
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
[SYNTHESIS_PARAM]
bench0_top = io_tc1
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench1_top = and2_latch
bench1_top = unsigned_mult_80
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench2_top = bin2bcd
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
@ -65,7 +62,7 @@ bench5_top = rs_decoder_top
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench6_top = top_module
bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench7_top = and2_or2
bench7_top = sha256
bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench8_top = cavlc_top
bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
@ -91,10 +88,6 @@ bench18_top = multi_enc_decx2x4
# sdc_controller requires 4 clocks
#bench19_top = sdc_controller
#bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench20_top = sha256
bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench21_top = unsigned_mult_80
bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=