update regression tests for split fabric_bitstream commands

openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose 
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose 
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose 
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga

@@ -38,7 +38,11 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.txt
+build_fabric_bitstream --verbose 
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Finish and exit OpenFPGA
 exit

openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga

@@ -43,7 +43,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga

@@ -43,7 +43,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream --format xml
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists

openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga

@@ -40,7 +40,10 @@ repack #--verbose
 build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file fabric_bitstream.xml --format xml
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist